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47 lines
835 B
Verilog
47 lines
835 B
Verilog
module calc_mean
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(
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input clock,
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input enable,
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input reset,
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input signed [15:0] a,
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input signed [15:0] b,
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input sign,
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input input_strobe,
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output reg signed [15:0] c,
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output reg output_strobe
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);
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reg signed [15:0] aa;
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reg signed [15:0] bb;
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reg signed [15:0] cc;
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reg [1:0] delay;
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reg [1:0] sign_stage;
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always @(posedge clock) begin
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if (reset) begin
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aa <= 0;
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bb <= 0;
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cc <= 0;
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c <= 0;
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output_strobe <= 0;
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delay <= 0;
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end else if (enable) begin
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delay[0] <= input_strobe;
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delay[1] <= delay[0];
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output_strobe <= delay[1];
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sign_stage[1] <= sign_stage[0];
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sign_stage[0] <= sign;
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aa <= a>>>1;
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bb <= b>>>1;
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cc <= aa + bb;
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c <= sign_stage[1]? ~cc+1: cc;
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end
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end
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endmodule
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