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33 lines
562 B
Verilog
33 lines
562 B
Verilog
module delayT
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#(
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parameter DATA_WIDTH = 32,
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parameter DELAY = 1
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)
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(
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input clock,
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input reset,
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input [DATA_WIDTH-1:0] data_in,
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output [DATA_WIDTH-1:0] data_out
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);
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reg [DATA_WIDTH-1:0] ram[DELAY-1:0];
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integer i;
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assign data_out = ram[DELAY-1];
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always @(posedge clock) begin
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if (reset) begin
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for (i = 0; i < DELAY; i = i+1) begin
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ram[i] <= 0;
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end
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end else begin
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ram[0] <= data_in;
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for (i = 1; i < DELAY; i= i+1) begin
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ram[i] <= ram[i-1];
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end
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end
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end
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endmodule
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