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67 lines
1.5 KiB
Verilog
67 lines
1.5 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module ram_2port
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#(
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parameter DWIDTH=32,
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parameter AWIDTH=9
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)
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(
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input clka,
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input ena,
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input wea,
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input [AWIDTH-1:0] addra,
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input [DWIDTH-1:0] dia,
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output reg [DWIDTH-1:0] doa,
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input clkb,
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input enb,
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input web,
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input [AWIDTH-1:0] addrb,
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input [DWIDTH-1:0] dib,
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output reg [DWIDTH-1:0] dob
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);
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reg [DWIDTH-1:0] ram [(1<<AWIDTH)-1:0];
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integer i;
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initial begin
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for(i=0;i<(1<<AWIDTH);i=i+1)
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ram[i] <= {DWIDTH{1'b0}};
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doa <= 0;
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dob <= 0;
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end
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always @(posedge clka) begin
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if (ena)
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begin
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if (wea)
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ram[addra] <= dia;
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doa <= ram[addra];
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end
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end
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always @(posedge clkb) begin
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if (enb)
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begin
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if (web)
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ram[addrb] <= dib;
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dob <= ram[addrb];
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end
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end
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endmodule // ram_2port
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