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openofdm
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8aa784707ac5e3bc2fc0c0f7b5fd324dc0534d07
openofdm
/
verilog
/
Xilinx
/
zynq
History
Xianjun Jiao
a7b95b492c
Workaround to supress the error message when the 1st time run simulation
2022-05-13 13:21:19 +02:00
..
atan_lut
phase estimation update: quadrant quantization from 256 slices -> 512 slices
2022-01-04 22:15:16 +01:00
complex_multiplier
extend support to zcu102/Zynq MPSoC ultra_scale
2020-04-27 15:46:16 +02:00
deinter_lut
Workaround to supress the error message when the 1st time run simulation
2022-05-13 13:21:19 +02:00
rot_lut
extend support to zcu102/Zynq MPSoC ultra_scale
2020-04-27 15:46:16 +02:00
viterbi
extend support to zcu102/Zynq MPSoC ultra_scale
2020-04-27 15:46:16 +02:00
xfft
extend support to zcu102/Zynq MPSoC ultra_scale
2020-04-27 15:46:16 +02:00
