mirror of
https://github.com/jhshi/openofdm.git
synced 2024-12-20 14:13:19 +00:00
340 lines
9.3 KiB
Verilog
340 lines
9.3 KiB
Verilog
`timescale 1ns/1ps
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module dot11_tb;
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`include "common_params.v"
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reg clock;
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reg reset;
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reg enable;
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reg [10:0] rssi_half_db;
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reg[31:0] sample_in;
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reg sample_in_strobe;
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reg [15:0] clk_count;
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wire [31:0] sync_short_metric;
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wire short_preamble_detected;
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wire power_trigger;
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wire [31:0] sync_long_out;
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wire sync_long_out_strobe;
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wire [31:0] sync_long_metric;
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wire sync_long_metric_stb;
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wire long_preamble_detected;
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wire [31:0] equalizer_out;
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wire equalizer_out_strobe;
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wire [5:0] demod_out;
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wire demod_out_strobe;
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wire [7:0] deinterleave_erase_out;
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wire deinterleave_erase_out_strobe;
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wire conv_decoder_out;
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wire conv_decoder_out_stb;
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wire descramble_out;
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wire descramble_out_strobe;
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wire [3:0] legacy_rate;
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wire legacy_sig_rsvd;
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wire [11:0] legacy_len;
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wire legacy_sig_parity;
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wire [5:0] legacy_sig_tail;
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wire legacy_sig_stb;
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reg signal_done;
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wire [3:0] dot11_state;
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wire pkt_header_valid_strobe;
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wire [7:0] byte_out;
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wire byte_out_strobe;
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wire [15:0] byte_count_total;
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wire [15:0] byte_count;
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wire [15:0] pkt_len_total;
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wire [15:0] pkt_len;
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wire [63:0] word_out;
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wire word_out_strobe;
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reg set_stb;
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reg [7:0] set_addr;
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reg [31:0] set_data;
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wire fcs_out_strobe, fcs_ok;
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integer addr;
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integer bb_sample_fd;
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integer power_trigger_fd;
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integer short_preamble_detected_fd;
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integer long_preamble_detected_fd;
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integer sync_long_metric_fd;
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integer sync_long_out_fd;
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integer equalizer_out_fd;
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integer demod_out_fd;
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integer deinterleave_erase_out_fd;
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integer conv_out_fd;
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integer descramble_out_fd;
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integer signal_fd;
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integer byte_out_fd;
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integer file_i, file_q, file_rssi_half_db, iq_sample_file;
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//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_65mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
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//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11a_48mbps_qos_data_e4_90_7e_15_2a_16_e8_de_27_90_6e_42_openwifi.txt"
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//`define NUM_SAMPLE 4560
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`define SAMPLE_FILE "../../../../../testing_inputs/simulated/openofdm_tx/PL_100Bytes/54Mbps.txt"
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`define NUM_SAMPLE 2048
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initial begin
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$dumpfile("dot11.vcd");
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$dumpvars;
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clock = 0;
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reset = 1;
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enable = 0;
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signal_done <= 0;
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# 20 reset = 0;
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enable = 1;
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set_stb = 1;
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# 20
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// do not skip sample
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set_addr = SR_SKIP_SAMPLE;
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set_data = 0;
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# 20 set_stb = 0;
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iq_sample_file = $fopen(`SAMPLE_FILE, "r");
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bb_sample_fd = $fopen("./sample_in.txt", "w");
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power_trigger_fd = $fopen("./power_trigger.txt", "w");
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short_preamble_detected_fd = $fopen("./short_preamble_detected.txt", "w");
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sync_long_metric_fd = $fopen("./sync_long_metric.txt", "w");
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long_preamble_detected_fd = $fopen("./sync_long_frame_detected.txt", "w");
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sync_long_out_fd = $fopen("./sync_long_out.txt", "w");
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equalizer_out_fd = $fopen("./equalizer_out.txt", "w");
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demod_out_fd = $fopen("./demod_out.txt", "w");
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deinterleave_erase_out_fd = $fopen("./deinterleave_erase_out.txt", "w");
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conv_out_fd = $fopen("./conv_out.txt", "w");
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descramble_out_fd = $fopen("./descramble_out.txt", "w");
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signal_fd = $fopen("./signal_out.txt", "w");
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byte_out_fd = $fopen("./byte_out.txt", "w");
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end
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always begin //200MHz
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#2.5 clock = !clock;
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end
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always @(posedge clock) begin
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if (reset) begin
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sample_in <= 0;
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clk_count <= 0;
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sample_in_strobe <= 0;
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addr <= 0;
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end else if (enable) begin
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if (clk_count == 9) begin
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sample_in_strobe <= 1;
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//$fscanf(iq_sample_file, "%d %d %d", file_i, file_q, file_rssi_half_db);
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$fscanf(iq_sample_file, "%d %d", file_i, file_q);
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sample_in[15:0] <= file_q;
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sample_in[31:16]<= file_i;
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//rssi_half_db <= file_rssi_half_db;
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rssi_half_db <= 0;
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addr <= addr + 1;
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clk_count <= 0;
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end else begin
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sample_in_strobe <= 0;
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clk_count <= clk_count + 1;
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end
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if (legacy_sig_stb) begin
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end
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//if (sample_in_strobe && power_trigger) begin
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if (sample_in_strobe) begin
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$fwrite(bb_sample_fd, "%d %d %d\n", $time/2, $signed(sample_in[31:16]), $signed(sample_in[15:0]));
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$fwrite(power_trigger_fd, "%d %d\n", $time/2, power_trigger);
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$fwrite(short_preamble_detected_fd, "%d %d\n", $time/2, short_preamble_detected);
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$fwrite(long_preamble_detected_fd, "%d %d\n", $time/2, long_preamble_detected);
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$fflush(bb_sample_fd);
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$fflush(power_trigger_fd);
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$fflush(short_preamble_detected_fd);
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$fflush(long_preamble_detected_fd);
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if ((addr % 100) == 0) begin
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$display("%d", addr);
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end
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if (addr == `NUM_SAMPLE) begin
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$fclose(iq_sample_file);
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$fclose(bb_sample_fd);
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$fclose(power_trigger_fd);
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$fclose(short_preamble_detected_fd);
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$fclose(sync_long_metric_fd);
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$fclose(long_preamble_detected_fd);
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$fclose(sync_long_out_fd);
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$fclose(equalizer_out_fd);
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$fclose(demod_out_fd);
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$fclose(deinterleave_erase_out_fd);
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$fclose(conv_out_fd);
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$fclose(descramble_out_fd);
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$fclose(signal_fd);
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$fclose(byte_out_fd);
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$finish;
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end
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end
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if (sync_long_metric_stb) begin
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$fwrite(sync_long_metric_fd, "%d %d\n", $time/2, sync_long_metric);
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$fflush(sync_long_metric_fd);
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end
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if (sync_long_out_strobe) begin
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$fwrite(sync_long_out_fd, "%d %d\n", $signed(sync_long_out[31:16]), $signed(sync_long_out[15:0]));
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$fflush(sync_long_out_fd);
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end
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if (equalizer_out_strobe) begin
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$fwrite(equalizer_out_fd, "%d %d\n", $signed(equalizer_out[31:16]), $signed(equalizer_out[15:0]));
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$fflush(equalizer_out_fd);
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end
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if (legacy_sig_stb) begin
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signal_done <= 1;
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$fwrite(signal_fd, "%04b %b %012b %b %06b", legacy_rate, legacy_sig_rsvd, legacy_len, legacy_sig_parity, legacy_sig_tail);
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$fflush(signal_fd);
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end
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if (dot11_state == S_DECODE_DATA && demod_out_strobe) begin
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$fwrite(demod_out_fd, "%b %b %b %b %b %b\n",demod_out[0],demod_out[1],demod_out[2],demod_out[3],demod_out[4],demod_out[5]);
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$fflush(demod_out_fd);
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end
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if (dot11_state == S_DECODE_DATA && deinterleave_erase_out_strobe) begin
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$fwrite(deinterleave_erase_out_fd, "%b %b %b %b %b %b %b %b\n", deinterleave_erase_out[0], deinterleave_erase_out[1], deinterleave_erase_out[2], deinterleave_erase_out[3], deinterleave_erase_out[4], deinterleave_erase_out[5], deinterleave_erase_out[6], deinterleave_erase_out[7]);
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$fflush(deinterleave_erase_out_fd);
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end
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if (dot11_state == S_DECODE_DATA && conv_decoder_out_stb) begin
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$fwrite(conv_out_fd, "%b\n", conv_decoder_out);
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$fflush(conv_out_fd);
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end
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if (dot11_state == S_DECODE_DATA && descramble_out_strobe) begin
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$fwrite(descramble_out_fd, "%b\n", descramble_out);
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$fflush(descramble_out_fd);
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end
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if (dot11_state == S_DECODE_DATA && byte_out_strobe) begin
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$fwrite(byte_out_fd, "%02x\n", byte_out);
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$fflush(byte_out_fd);
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end
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end
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end
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dot11 dot11_inst (
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.clock(clock),
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.reset(reset),
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.enable(enable),
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//.set_stb(set_stb),
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//.set_addr(set_addr),
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//.set_data(set_data),
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.power_thres(11'd0),
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.min_plateau(32'd100),
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.rssi_half_db(rssi_half_db),
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.sample_in(sample_in),
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.sample_in_strobe(sample_in_strobe),
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.state(dot11_state),
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.power_trigger(power_trigger),
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.short_preamble_detected(short_preamble_detected),
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.sync_long_metric(sync_long_metric),
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.sync_long_metric_stb(sync_long_metric_stb),
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.long_preamble_detected(long_preamble_detected),
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.sync_long_out(sync_long_out),
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.sync_long_out_strobe(sync_long_out_strobe),
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.equalizer_out(equalizer_out),
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.equalizer_out_strobe(equalizer_out_strobe),
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.demod_out(demod_out),
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.demod_out_strobe(demod_out_strobe),
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.deinterleave_erase_out(deinterleave_erase_out),
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.deinterleave_erase_out_strobe(deinterleave_erase_out_strobe),
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.conv_decoder_out(conv_decoder_out),
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.conv_decoder_out_stb(conv_decoder_out_stb),
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.descramble_out(descramble_out),
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.descramble_out_strobe(descramble_out_strobe),
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.pkt_header_valid_strobe(pkt_header_valid_strobe),
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.byte_out(byte_out),
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.byte_out_strobe(byte_out_strobe),
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.fcs_out_strobe(fcs_out_strobe),
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.fcs_ok(fcs_ok),
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.byte_count_total(byte_count_total),
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.byte_count(byte_count),
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.pkt_len_total(pkt_len_total),
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.pkt_len(pkt_len),
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.legacy_rate(legacy_rate),
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.legacy_sig_rsvd(legacy_sig_rsvd),
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.legacy_len(legacy_len),
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.legacy_sig_parity(legacy_sig_parity),
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.legacy_sig_tail(legacy_sig_tail),
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.legacy_sig_stb(legacy_sig_stb)
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);
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byte_to_word_fcs_sn_insert byte_to_word_fcs_sn_insert_inst (
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.clk(clock),
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.rstn((~reset)&(~pkt_header_valid_strobe)),
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.byte_in(byte_out),
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.byte_in_strobe(byte_out_strobe),
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.byte_count(byte_count),
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.num_byte(pkt_len),
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.fcs_in_strobe(fcs_out_strobe),
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.fcs_ok(fcs_ok),
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.rx_pkt_sn_plus_one(0),
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.word_out(word_out),
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.word_out_strobe(word_out_strobe)
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);
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endmodule
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