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68 lines
1.0 KiB
Verilog
68 lines
1.0 KiB
Verilog
module complex_mult
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(
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input clock,
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input enable,
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input reset,
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input [15:0] a_i,
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input [15:0] a_q,
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input [15:0] b_i,
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input [15:0] b_q,
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input input_strobe,
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output reg [31:0] p_i,
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output reg [31:0] p_q,
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output output_strobe
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);
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localparam DELAY = 4;
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reg [DELAY-1:0] delay;
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reg [15:0] ar;
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reg [15:0] ai;
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reg [15:0] br;
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reg [15:0] bi;
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wire [31:0] prod_i;
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wire [31:0] prod_q;
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complex_multiplier mult_inst (
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.clk(clock),
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.ar(ar),
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.ai(ai),
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.br(br),
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.bi(bi),
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.pr(prod_i),
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.pi(prod_q)
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);
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delayT #(.DATA_WIDTH(1), .DELAY(5)) stb_delay_inst (
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.clock(clock),
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.reset(reset),
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.data_in(input_strobe),
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.data_out(output_strobe)
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);
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always @(posedge clock) begin
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if (reset) begin
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ar <= 0;
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ai <= 0;
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br <= 0;
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bi <= 0;
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p_i <= 0;
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p_q <= 0;
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delay <= 0;
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end else if (enable) begin
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ar <= a_i;
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ai <= a_q;
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br <= b_i;
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bi <= b_q;
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p_i <= prod_i;
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p_q <= prod_q;
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end
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end
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endmodule
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