mirror of
https://github.com/jhshi/openofdm.git
synced 2024-12-20 06:08:11 +00:00
629 lines
18 KiB
Verilog
629 lines
18 KiB
Verilog
`include "openofdm_rx_pre_def.v"
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`timescale 1ns/1ps
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module dot11_side_ch_tb;
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`include "common_params.v"
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localparam integer TSF_TIMER_WIDTH = 64; // according to 802.11 standard
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localparam integer GPIO_STATUS_WIDTH = 8;
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localparam integer RSSI_HALF_DB_WIDTH = 11;
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localparam integer ADC_PACK_DATA_WIDTH = 64;
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localparam integer IQ_DATA_WIDTH = 16;
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localparam integer RSSI_DATA_WIDTH = 10;
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localparam integer C_S00_AXI_DATA_WIDTH = 32;
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localparam integer C_S00_AXI_ADDR_WIDTH = 7;
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localparam integer C_S00_AXIS_TDATA_WIDTH = 64;
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localparam integer C_M00_AXIS_TDATA_WIDTH = 64;
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localparam integer WAIT_COUNT_BITS = 5;
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localparam integer MAX_NUM_DMA_SYMBOL = 8192; // the fifo depth inside m_axis
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function integer clogb2 (input integer bit_depth);
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begin
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for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
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bit_depth = bit_depth >> 1;
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end
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endfunction
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localparam integer MAX_BIT_NUM_DMA_SYMBOL = clogb2(MAX_NUM_DMA_SYMBOL);
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reg clock;
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reg reset;
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reg enable;
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reg [10:0] rssi_half_db;
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reg[31:0] sample_in;
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reg sample_in_strobe;
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reg [15:0] clk_count;
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wire [31:0] sync_short_metric;
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wire short_preamble_detected;
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wire power_trigger;
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wire [31:0] sync_long_out;
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wire sync_long_out_strobe;
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wire [31:0] sync_long_metric;
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wire sync_long_metric_stb;
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wire long_preamble_detected;
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wire [31:0] phase_offset_taken;
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wire [31:0] equalizer_out;
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wire equalizer_out_strobe;
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wire [5:0] demod_out;
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wire demod_out_strobe;
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wire [7:0] deinterleave_erase_out;
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wire deinterleave_erase_out_strobe;
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wire conv_decoder_out;
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wire conv_decoder_out_stb;
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wire descramble_out;
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wire descramble_out_strobe;
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wire [3:0] legacy_rate;
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wire legacy_sig_rsvd;
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wire [11:0] legacy_len;
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wire legacy_sig_parity;
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wire [5:0] legacy_sig_tail;
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wire legacy_sig_stb;
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reg signal_done;
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wire [3:0] dot11_state;
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wire pkt_header_valid;
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wire pkt_header_valid_strobe;
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wire [7:0] byte_out;
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wire byte_out_strobe;
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wire [15:0] byte_count_total;
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wire [15:0] byte_count;
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wire [15:0] pkt_len_total;
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wire [15:0] pkt_len;
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// wire [63:0] word_out;
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// wire word_out_strobe;
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wire demod_is_ongoing;
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wire ofdm_symbol_eq_out_pulse;
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wire ht_unsupport;
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wire [7:0] pkt_rate;
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wire [(32-1):0] csi;
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wire csi_valid;
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wire [31:0] FC_DI;
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wire FC_DI_valid;
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wire [47:0] addr1;
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wire addr1_valid;
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wire [47:0] addr2;
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wire addr2_valid;
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wire [47:0] addr3;
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wire addr3_valid;
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wire m_axis_start_1trans;
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wire [63:0] data_to_ps;
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wire data_to_ps_valid;
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wire [(MAX_BIT_NUM_DMA_SYMBOL-1):0] m_axis_data_count;
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wire fulln_to_pl;
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wire M_AXIS_TVALID;
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wire M_AXIS_TLAST;
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reg slv_reg_wren_signal;
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reg [4:0] axi_awaddr_core;
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reg [3:0] num_eq;
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// iq capture configuration
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reg iq_capture;
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reg [3:0] iq_trigger_select;
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reg signed [(RSSI_HALF_DB_WIDTH-1):0] rssi_th;
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reg [(GPIO_STATUS_WIDTH-2):0] gain_th;
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reg [MAX_BIT_NUM_DMA_SYMBOL-1 : 0] pre_trigger_len;
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reg [MAX_BIT_NUM_DMA_SYMBOL-1 : 0] iq_len_target;
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reg set_stb;
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reg [7:0] set_addr;
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reg [31:0] set_data;
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wire fcs_out_strobe, fcs_ok;
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integer addr;
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integer bb_sample_fd;
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integer power_trigger_fd;
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integer short_preamble_detected_fd;
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integer long_preamble_detected_fd;
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integer sync_long_metric_fd;
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integer sync_long_out_fd;
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integer equalizer_out_fd;
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integer demod_out_fd;
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integer deinterleave_erase_out_fd;
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integer conv_out_fd;
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integer descramble_out_fd;
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integer signal_fd;
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integer byte_out_fd;
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integer file_i, file_q, file_rssi_half_db, iq_sample_file;
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`define SPEED_100M // remove this to use 200M
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localparam integer IQ_CAPTURE = 1; //0 -- CSI; 1 -- IQ
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localparam integer IQ_TRIGGER_SELECT = 6;
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localparam integer PRE_TRIGGER_LEN = 3;
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localparam integer IQ_LEN_TARGET = 7;
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//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_ht_unsupport_openwifi.txt"
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//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_wrong_ht_sig_openwifi.txt"
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//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_wrong_sig_openwifi.txt"
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//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_openwifi.txt"
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// `define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_6.5mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
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// `define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_52mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
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// `define SAMPLE_FILE "../../../../../testing_inputs/radiated/dot11n_19.5mbps_openwifi.txt"
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//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_58.5mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
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// `define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_65mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
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// `define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11a_48mbps_qos_data_e4_90_7e_15_2a_16_e8_de_27_90_6e_42_openwifi.txt"
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//`define SAMPLE_FILE "../../../../../testing_inputs/radiated/ack-ok-openwifi.txt"
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`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_mixed_for_side_ch_openwifi.txt"
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`define NUM_SAMPLE 18560
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//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/openofdm_tx/PL_100Bytes/54Mbps.txt"
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//`define NUM_SAMPLE 2048
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initial begin
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$dumpfile("dot11.vcd");
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$dumpvars;
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slv_reg_wren_signal = 0;
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axi_awaddr_core = 0;
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iq_capture = IQ_CAPTURE;
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iq_trigger_select = IQ_TRIGGER_SELECT;
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rssi_th = 0;
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gain_th = 0;
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pre_trigger_len = PRE_TRIGGER_LEN;
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iq_len_target = IQ_LEN_TARGET;
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clock = 0;
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reset = 1;
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enable = 0;
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signal_done <= 0;
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# 20 reset = 0;
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enable = 1;
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set_stb = 1;
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# 20
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// do not skip sample
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set_addr = SR_SKIP_SAMPLE;
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set_data = 0;
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# 20 set_stb = 0;
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end
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integer file_open_trigger = 0;
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always @(posedge clock) begin
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file_open_trigger = file_open_trigger + 1;
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if (file_open_trigger==1) begin
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iq_sample_file = $fopen(`SAMPLE_FILE, "r");
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bb_sample_fd = $fopen("./sample_in.txt", "w");
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power_trigger_fd = $fopen("./power_trigger.txt", "w");
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short_preamble_detected_fd = $fopen("./short_preamble_detected.txt", "w");
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sync_long_metric_fd = $fopen("./sync_long_metric.txt", "w");
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long_preamble_detected_fd = $fopen("./sync_long_frame_detected.txt", "w");
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sync_long_out_fd = $fopen("./sync_long_out.txt", "w");
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equalizer_out_fd = $fopen("./equalizer_out.txt", "w");
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demod_out_fd = $fopen("./demod_out.txt", "w");
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deinterleave_erase_out_fd = $fopen("./deinterleave_erase_out.txt", "w");
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conv_out_fd = $fopen("./conv_out.txt", "w");
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descramble_out_fd = $fopen("./descramble_out.txt", "w");
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signal_fd = $fopen("./signal_out.txt", "w");
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byte_out_fd = $fopen("./byte_out.txt", "w");
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end
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end
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`ifdef SPEED_100M
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always begin //100MHz
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#5 clock = !clock;
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end
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`else
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always begin //200MHz
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#2.5 clock = !clock;
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end
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`endif
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always @(posedge clock) begin
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if (reset) begin
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sample_in <= 0;
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clk_count <= 0;
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sample_in_strobe <= 0;
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addr <= 0;
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num_eq <= 5;
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end else if (enable) begin
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`ifdef SPEED_100M
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if (clk_count == 4) begin // for 100M; 100/20 = 5
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`else
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if (clk_count == 9) begin // for 200M; 200/20 = 10
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`endif
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sample_in_strobe <= 1;
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//$fscanf(iq_sample_file, "%d %d %d", file_i, file_q, file_rssi_half_db);
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$fscanf(iq_sample_file, "%d %d", file_i, file_q);
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sample_in[15:0] <= file_q;
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sample_in[31:16]<= file_i;
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//rssi_half_db <= file_rssi_half_db;
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rssi_half_db <= 0;
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addr <= addr + 1;
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clk_count <= 0;
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end else begin
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sample_in_strobe <= 0;
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clk_count <= clk_count + 1;
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end
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if (short_preamble_detected) begin
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num_eq <= num_eq + 3;
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end
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if (legacy_sig_stb) begin
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end
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//if (sample_in_strobe && power_trigger) begin
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if (sample_in_strobe) begin
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$fwrite(bb_sample_fd, "%d %d %d\n", $time/2, $signed(sample_in[31:16]), $signed(sample_in[15:0]));
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$fwrite(power_trigger_fd, "%d %d\n", $time/2, power_trigger);
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$fwrite(short_preamble_detected_fd, "%d %d\n", $time/2, short_preamble_detected);
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$fwrite(long_preamble_detected_fd, "%d %d\n", $time/2, long_preamble_detected);
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$fflush(bb_sample_fd);
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$fflush(power_trigger_fd);
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$fflush(short_preamble_detected_fd);
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$fflush(long_preamble_detected_fd);
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if ((addr % 100) == 0) begin
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$display("%d", addr);
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end
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if (addr == `NUM_SAMPLE) begin
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$fclose(iq_sample_file);
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$fclose(bb_sample_fd);
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$fclose(power_trigger_fd);
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$fclose(short_preamble_detected_fd);
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$fclose(sync_long_metric_fd);
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$fclose(long_preamble_detected_fd);
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$fclose(sync_long_out_fd);
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$fclose(equalizer_out_fd);
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$fclose(demod_out_fd);
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$fclose(deinterleave_erase_out_fd);
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$fclose(conv_out_fd);
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$fclose(descramble_out_fd);
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$fclose(signal_fd);
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$fclose(byte_out_fd);
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$finish;
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end
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end
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if (sync_long_metric_stb) begin
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$fwrite(sync_long_metric_fd, "%d %d\n", $time/2, sync_long_metric);
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$fflush(sync_long_metric_fd);
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end
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if (sync_long_out_strobe) begin
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$fwrite(sync_long_out_fd, "%d %d\n", $signed(sync_long_out[31:16]), $signed(sync_long_out[15:0]));
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$fflush(sync_long_out_fd);
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end
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if (equalizer_out_strobe) begin
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$fwrite(equalizer_out_fd, "%d %d\n", $signed(equalizer_out[31:16]), $signed(equalizer_out[15:0]));
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$fflush(equalizer_out_fd);
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end
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if (legacy_sig_stb) begin
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signal_done <= 1;
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$fwrite(signal_fd, "%04b %b %012b %b %06b", legacy_rate, legacy_sig_rsvd, legacy_len, legacy_sig_parity, legacy_sig_tail);
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$fflush(signal_fd);
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end
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if (dot11_state == S_DECODE_DATA && demod_out_strobe) begin
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$fwrite(demod_out_fd, "%b %b %b %b %b %b\n",demod_out[0],demod_out[1],demod_out[2],demod_out[3],demod_out[4],demod_out[5]);
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$fflush(demod_out_fd);
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end
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if (dot11_state == S_DECODE_DATA && deinterleave_erase_out_strobe) begin
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$fwrite(deinterleave_erase_out_fd, "%b %b %b %b %b %b %b %b\n", deinterleave_erase_out[0], deinterleave_erase_out[1], deinterleave_erase_out[2], deinterleave_erase_out[3], deinterleave_erase_out[4], deinterleave_erase_out[5], deinterleave_erase_out[6], deinterleave_erase_out[7]);
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$fflush(deinterleave_erase_out_fd);
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end
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if (dot11_state == S_DECODE_DATA && conv_decoder_out_stb) begin
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$fwrite(conv_out_fd, "%b\n", conv_decoder_out);
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$fflush(conv_out_fd);
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end
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if (dot11_state == S_DECODE_DATA && descramble_out_strobe) begin
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$fwrite(descramble_out_fd, "%b\n", descramble_out);
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$fflush(descramble_out_fd);
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end
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if (dot11_state == S_DECODE_DATA && byte_out_strobe) begin
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$fwrite(byte_out_fd, "%02x\n", byte_out);
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$fflush(byte_out_fd);
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end
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end
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end
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side_ch_control # (
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.TSF_TIMER_WIDTH(TSF_TIMER_WIDTH), // according to 802.11 standard
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.GPIO_STATUS_WIDTH(GPIO_STATUS_WIDTH),
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.RSSI_HALF_DB_WIDTH(RSSI_HALF_DB_WIDTH),
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.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
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.IQ_DATA_WIDTH(IQ_DATA_WIDTH),
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.C_S_AXIS_TDATA_WIDTH(C_S00_AXIS_TDATA_WIDTH),
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.MAX_NUM_DMA_SYMBOL(MAX_NUM_DMA_SYMBOL),
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.MAX_BIT_NUM_DMA_SYMBOL(MAX_BIT_NUM_DMA_SYMBOL)
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) side_ch_control_i (
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.clk(clock),
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.rstn(~reset),
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// from pl
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.gpio_status(34),
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.rssi_half_db(54),
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.tsf_runtime_val(64'd123456),
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.iq(sample_in),
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.iq_strobe(sample_in_strobe),
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.demod_is_ongoing(demod_is_ongoing),
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.ofdm_symbol_eq_out_pulse(ofdm_symbol_eq_out_pulse),
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.long_preamble_detected(long_preamble_detected),
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.short_preamble_detected(short_preamble_detected),
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.ht_unsupport(ht_unsupport),
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.pkt_rate(pkt_rate),
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.pkt_len(pkt_len),
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.csi(csi),
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.csi_valid(csi_valid),
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.phase_offset_taken(phase_offset_taken),
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.equalizer(equalizer_out),
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.equalizer_valid(equalizer_out_strobe),
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.pkt_header_valid(pkt_header_valid),
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.pkt_header_valid_strobe(pkt_header_valid_strobe),
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.FC_DI(FC_DI),
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.FC_DI_valid(FC_DI_valid),
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.addr1(addr1),
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.addr1_valid(addr1_valid),
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.addr2(addr2),
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.addr2_valid(addr2_valid),
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.addr3(addr3),
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.addr3_valid(addr3_valid),
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.fcs_in_strobe(fcs_out_strobe),
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.fcs_ok(fcs_ok),
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.block_rx_dma_to_ps(),
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.block_rx_dma_to_ps_valid(),
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// from arm
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.slv_reg_wren_signal(slv_reg_wren_signal), // to capture m axis num dma symbol write, so that auto trigger start
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.axi_awaddr_core(axi_awaddr_core),
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.iq_capture(iq_capture),
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.iq_trigger_select(iq_trigger_select),
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.rssi_th(rssi_th),
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.gain_th(gain_th),
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.pre_trigger_len(pre_trigger_len),
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.iq_len_target(iq_len_target),
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.FC_target(16'd3243),
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.addr1_target(32'd23343),
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.addr2_target(32'd98765),
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.match_cfg(0),
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.num_eq({1'd0, num_eq[2:0]}),
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.m_axis_start_mode(1),
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.m_axis_start_ext_trigger(),
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// s_axis
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.data_to_pl(),
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.pl_ask_data(),
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.s_axis_data_count(),
|
|
.emptyn_to_pl(),
|
|
|
|
.S_AXIS_TVALID(),
|
|
.S_AXIS_TLAST(),
|
|
|
|
// m_axis
|
|
.m_axis_start_1trans(m_axis_start_1trans),
|
|
|
|
.data_to_ps(data_to_ps),
|
|
.data_to_ps_valid(data_to_ps_valid),
|
|
.m_axis_data_count(m_axis_data_count),
|
|
.fulln_to_pl(fulln_to_pl),
|
|
|
|
.M_AXIS_TVALID(M_AXIS_TVALID),
|
|
.M_AXIS_TLAST(M_AXIS_TLAST)
|
|
);
|
|
|
|
side_ch_m_axis # (
|
|
// .WAIT_COUNT_BITS(WAIT_COUNT_BITS),
|
|
.MAX_NUM_DMA_SYMBOL(MAX_NUM_DMA_SYMBOL),
|
|
.MAX_BIT_NUM_DMA_SYMBOL(MAX_BIT_NUM_DMA_SYMBOL),
|
|
.C_M_AXIS_TDATA_WIDTH(C_M00_AXIS_TDATA_WIDTH)
|
|
) side_ch_m_axis_i (
|
|
.m_axis_endless_mode(0),
|
|
.M_AXIS_NUM_DMA_SYMBOL(3222-1),
|
|
|
|
.m_axis_start_1trans(m_axis_start_1trans),
|
|
|
|
.data_to_ps(data_to_ps),
|
|
.data_to_ps_valid(data_to_ps_valid),
|
|
.m_axis_data_count(m_axis_data_count),
|
|
.fulln_to_pl(fulln_to_pl),
|
|
|
|
.M_AXIS_ACLK(clock),
|
|
.M_AXIS_ARESETN( ~reset ),
|
|
.M_AXIS_TVALID(M_AXIS_TVALID),
|
|
.M_AXIS_TDATA(),
|
|
.M_AXIS_TSTRB(),
|
|
.M_AXIS_TLAST(M_AXIS_TLAST),
|
|
.M_AXIS_TREADY(1)
|
|
);
|
|
|
|
phy_rx_parse phy_rx_parse_inst (
|
|
.clk(clock),
|
|
.rstn( ~reset ),
|
|
|
|
.ofdm_byte_index(byte_count),
|
|
.ofdm_byte(byte_out),
|
|
.ofdm_byte_valid(byte_out_strobe),
|
|
|
|
.FC_DI(FC_DI),
|
|
.FC_DI_valid(FC_DI_valid),
|
|
|
|
.rx_addr(addr1),
|
|
.rx_addr_valid(addr1_valid),
|
|
|
|
.dst_addr(addr2),
|
|
.dst_addr_valid(addr2_valid),
|
|
|
|
.tx_addr(addr3),
|
|
.tx_addr_valid(addr3_valid),
|
|
|
|
.SC(),
|
|
.SC_valid(),
|
|
|
|
.src_addr(),
|
|
.src_addr_valid()
|
|
);
|
|
|
|
dot11 dot11_inst (
|
|
.clock(clock),
|
|
.enable(enable),
|
|
.reset(reset),
|
|
|
|
//.set_stb(set_stb),
|
|
//.set_addr(set_addr),
|
|
//.set_data(set_data),
|
|
|
|
.power_thres(11'd0),
|
|
.min_plateau(32'd100),
|
|
|
|
.rssi_half_db(rssi_half_db),
|
|
.sample_in(sample_in),
|
|
.sample_in_strobe(sample_in_strobe),
|
|
.soft_decoding(1'b1),
|
|
|
|
.demod_is_ongoing(demod_is_ongoing),
|
|
.pkt_begin(pkt_begin),
|
|
.pkt_ht(pkt_ht),
|
|
.pkt_header_valid(pkt_header_valid),
|
|
.pkt_header_valid_strobe(pkt_header_valid_strobe),
|
|
.ht_unsupport(ht_unsupport),
|
|
.pkt_rate(pkt_rate),
|
|
.pkt_len(pkt_len),
|
|
.pkt_len_total(pkt_len_total),
|
|
.byte_out_strobe(byte_out_strobe),
|
|
.byte_out(byte_out),
|
|
.byte_count_total(byte_count_total),
|
|
.byte_count(byte_count),
|
|
.fcs_out_strobe(fcs_out_strobe),
|
|
.fcs_ok(fcs_ok),
|
|
|
|
.state(dot11_state),
|
|
.status_code(status_code),
|
|
.state_changed(state_changed),
|
|
.state_history(state_history),
|
|
|
|
.power_trigger(power_trigger),
|
|
|
|
.short_preamble_detected(short_preamble_detected),
|
|
.phase_offset(phase_offset),
|
|
|
|
.sync_long_metric(sync_long_metric),
|
|
.sync_long_metric_stb(sync_long_metric_stb),
|
|
.long_preamble_detected(long_preamble_detected),
|
|
.sync_long_out(sync_long_out),
|
|
.sync_long_out_strobe(sync_long_out_strobe),
|
|
.phase_offset_taken(phase_offset_taken),
|
|
.sync_long_state(sync_long_state),
|
|
|
|
.equalizer_out(equalizer_out),
|
|
.equalizer_out_strobe(equalizer_out_strobe),
|
|
.equalizer_state(equalizer_state),
|
|
.ofdm_symbol_eq_out_pulse(ofdm_symbol_eq_out_pulse),
|
|
|
|
.legacy_sig_stb(legacy_sig_stb),
|
|
.legacy_rate(legacy_rate),
|
|
.legacy_sig_rsvd(legacy_sig_rsvd),
|
|
.legacy_len(legacy_len),
|
|
.legacy_sig_parity(legacy_sig_parity),
|
|
.legacy_sig_parity_ok(legacy_sig_parity_ok),
|
|
.legacy_sig_tail(legacy_sig_tail),
|
|
|
|
.ht_sig_stb(ht_sig_stb),
|
|
.ht_mcs(ht_mcs),
|
|
.ht_cbw(ht_cbw),
|
|
.ht_len(ht_len),
|
|
.ht_smoothing(ht_smoothing),
|
|
.ht_not_sounding(ht_not_sounding),
|
|
.ht_aggregation(ht_aggregation),
|
|
.ht_stbc(ht_stbc),
|
|
.ht_fec_coding(ht_fec_coding),
|
|
.ht_sgi(ht_sgi),
|
|
.ht_num_ext(ht_num_ext),
|
|
.ht_sig_crc_ok(ht_sig_crc_ok),
|
|
|
|
.demod_out(demod_out),
|
|
.demod_out_strobe(demod_out_strobe),
|
|
|
|
.deinterleave_erase_out(deinterleave_erase_out),
|
|
.deinterleave_erase_out_strobe(deinterleave_erase_out_strobe),
|
|
|
|
.conv_decoder_out(conv_decoder_out),
|
|
.conv_decoder_out_stb(conv_decoder_out_stb),
|
|
|
|
.csi(csi),
|
|
.csi_valid(csi_valid),
|
|
|
|
.descramble_out(descramble_out),
|
|
.descramble_out_strobe(descramble_out_strobe)
|
|
);
|
|
|
|
/*
|
|
byte_to_word_fcs_sn_insert byte_to_word_fcs_sn_insert_inst (
|
|
.clk(clock),
|
|
.rstn((~reset)&(~pkt_header_valid_strobe)),
|
|
|
|
.byte_in(byte_out),
|
|
.byte_in_strobe(byte_out_strobe),
|
|
.byte_count(byte_count),
|
|
.num_byte(pkt_len),
|
|
.fcs_in_strobe(fcs_out_strobe),
|
|
.fcs_ok(fcs_ok),
|
|
.rx_pkt_sn_plus_one(0),
|
|
|
|
.word_out(word_out),
|
|
.word_out_strobe(word_out_strobe)
|
|
);
|
|
*/
|
|
|
|
endmodule
|