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82 lines
2.4 KiB
Verilog
82 lines
2.4 KiB
Verilog
module complex_mult
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(
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input clock,
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input enable,
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input reset,
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input [15:0] a_i,
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input [15:0] a_q,
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input [15:0] b_i,
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input [15:0] b_q,
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input input_strobe,
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output [31:0] p_i,
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output [31:0] p_q,
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output output_strobe
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);
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wire [63:0] m_axis_dout_tdata;
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assign p_q = m_axis_dout_tdata[63:32];
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assign p_i = m_axis_dout_tdata[31:0];
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complex_multiplier mult_inst (
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.aclk(clock), // input wire aclk
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.s_axis_a_tvalid(input_strobe), // input wire s_axis_a_tvalid
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.s_axis_a_tdata({a_q, a_i}), // input wire [31 : 0] s_axis_a_tdata
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.s_axis_b_tvalid(input_strobe), // input wire s_axis_b_tvalid
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.s_axis_b_tdata({b_q, b_i}), // input wire [31 : 0] s_axis_b_tdata
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.m_axis_dout_tvalid(output_strobe), // output wire m_axis_dout_tvalid
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.m_axis_dout_tdata(m_axis_dout_tdata) // output wire [63 : 0] m_axis_dout_tdata
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);
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// reg [15:0] ar;
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// reg [15:0] ai;
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// reg [15:0] br;
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// reg [15:0] bi;
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// wire [31:0] prod_i;
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// wire [31:0] prod_q;
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// // instantiation of complex multiplier
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// wire [31:0] s_axis_a_tdata;
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// assign s_axis_a_tdata = {ai,ar} ;
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// wire [31:0] s_axis_b_tdata;
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// assign s_axis_b_tdata = {bi, br} ;
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// wire [63:0] m_axis_dout_tdata;
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// assign prod_q = m_axis_dout_tdata[63:32];
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// assign prod_i = m_axis_dout_tdata[31:0];
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// wire m_axis_dout_tvalid ;
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// assign output_strobe = m_axis_dout_tvalid; //output strobe valid at the beginning of new data -- simulation confirmed
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// complex_multiplier mult_inst (
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// .aclk(clock), // input wire aclk
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// .s_axis_a_tvalid(input_strobe), // input wire s_axis_a_tvalid
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// .s_axis_a_tdata(s_axis_a_tdata), // input wire [31 : 0] s_axis_a_tdata
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// .s_axis_b_tvalid(input_strobe), // input wire s_axis_b_tvalid
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// .s_axis_b_tdata(s_axis_b_tdata), // input wire [31 : 0] s_axis_b_tdata
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// .m_axis_dout_tvalid(m_axis_dout_tvalid), // output wire m_axis_dout_tvalid
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// .m_axis_dout_tdata(m_axis_dout_tdata) // output wire [63 : 0] m_axis_dout_tdata
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// );
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// always @(posedge clock) begin
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// if (reset) begin
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// ar <= 0;
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// ai <= 0;
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// br <= 0;
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// bi <= 0;
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// p_i <= 0;
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// p_q <= 0;
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// end else if (enable) begin
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// ar <= a_i;
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// ai <= a_q;
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// br <= b_i;
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// bi <= b_q;
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// p_i <= prod_i;
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// p_q <= prod_q;
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// end
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// end
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endmodule
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