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openofdm/verilog/Xilinx/zynquplus/viterbi/viterbi_v7_0.xci
Xianjun Jiao abbe9ecde9 extend support to zcu102/Zynq MPSoC ultra_scale
2020-04-27 15:46:16 +02:00

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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Puncturing" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reduced_Latency" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TREADY" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Traceback_Length" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
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