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48 lines
852 B
Verilog
48 lines
852 B
Verilog
module complex_to_mag_sq (
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input clock,
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input enable,
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input reset,
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input signed [15:0] i,
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input signed [15:0] q,
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input input_strobe,
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output [31:0] mag_sq,
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output mag_sq_strobe
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);
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reg valid_in;
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reg [15:0] input_i;
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reg [15:0] input_q;
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reg [15:0] input_q_neg;
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complex_mult mult_inst (
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.clock(clock),
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.reset(reset),
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.enable(enable),
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.a_i(input_i),
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.a_q(input_q),
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.b_i(input_i),
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.b_q(input_q_neg),
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.input_strobe(valid_in),
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.p_i(mag_sq),
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.output_strobe(mag_sq_strobe)
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);
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always @(posedge clock) begin
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if (reset) begin
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input_i <= 0;
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input_q <= 0;
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input_q_neg <= 0;
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valid_in <= 0;
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end else if (enable) begin
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valid_in <= input_strobe;
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input_i <= i;
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input_q <= q;
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input_q_neg <= ~q+1;
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end
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end
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endmodule
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