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38 lines
747 B
Verilog
38 lines
747 B
Verilog
module bits_to_bytes
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(
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input clock,
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input enable,
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input reset,
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input bit_in,
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input input_strobe,
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output reg [7:0] byte_out,
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output reg output_strobe
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);
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reg [7:0] bit_buf;
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reg [2:0] addr;
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always @(posedge clock) begin
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if (reset) begin
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addr <= 0;
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bit_buf <= 0;
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byte_out <= 0;
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output_strobe <= 0;
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end else if (enable & input_strobe) begin
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bit_buf[7] <= bit_in;
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bit_buf[6:0] <= bit_buf[7:1];
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addr <= addr + 1;
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if (addr == 7) begin
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byte_out <= {bit_in, bit_buf[7:1]};
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output_strobe <= 1;
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end else begin
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output_strobe <= 0;
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end
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end else begin
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output_strobe <= 0;
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end
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end
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endmodule
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