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132 lines
3.0 KiB
Verilog
132 lines
3.0 KiB
Verilog
`include "common_defs.v"
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module phase
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#(
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parameter DATA_WIDTH = 32
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)
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(
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input clock,
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input reset,
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input enable,
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input signed [DATA_WIDTH-1:0] in_i,
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input signed [DATA_WIDTH-1:0] in_q,
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input input_strobe,
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// [-pi, pi) scaled up by 2048
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output reg signed [31:0] phase,
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output output_strobe
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);
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`include "common_params.v"
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reg [DATA_WIDTH-1:0] in_i_delay;
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reg [DATA_WIDTH-1:0] in_q_delay;
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reg [DATA_WIDTH-1:0] abs_i;
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reg [DATA_WIDTH-1:0] abs_q;
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reg [DATA_WIDTH-1:0] max;
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reg [DATA_WIDTH-1:0] min;
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wire div_in_stb;
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wire [31:0] quotient;
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wire div_out_stb;
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wire [`ATAN_LUT_LEN_SHIFT-1:0] atan_addr;
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wire [`ATAN_LUT_SCALE_SHIFT-1:0] atan_data;
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assign atan_addr = quotient[`ATAN_LUT_LEN_SHIFT-1:0];
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wire signed [`ATAN_LUT_SCALE_SHIFT:0] _phase = {1'b0, atan_data};
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reg [2:0] quadrant;
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wire [2:0] quadrant_delayed;
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// 1 cycle for abs
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// 1 cycle for quadrant
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delayT #(.DATA_WIDTH(1), .DELAY(2)) div_in_inst (
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.clock(clock),
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.reset(reset),
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.data_in(input_strobe),
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.data_out(div_in_stb)
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);
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// 1 cycle for atan_lut
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// 1 cycle for quadrant_delayed
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delayT #(.DATA_WIDTH(1), .DELAY(2)) output_inst (
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.clock(clock),
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.reset(reset),
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.data_in(div_out_stb),
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.data_out(output_strobe)
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);
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divider div_inst (
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.clock(clock),
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.enable(enable),
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.reset(reset),
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.dividend(min),
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.divisor({{(`ATAN_LUT_LEN_SHIFT-8){1'b0}}, max[31:`ATAN_LUT_LEN_SHIFT]}),
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.input_strobe(div_in_stb),
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.quotient(quotient),
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.output_strobe(div_out_stb)
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);
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delayT #(.DATA_WIDTH(3), .DELAY(36)) quadrant_inst (
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.clock(clock),
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.reset(reset),
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.data_in(quadrant),
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.data_out(quadrant_delayed)
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);
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atan_lut lut_inst (
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.clka(clock),
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.addra(atan_addr),
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.douta(atan_data)
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);
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always @(posedge clock) begin
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if (reset) begin
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max <= 0;
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min <= 0;
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abs_i <= 0;
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abs_q <= 0;
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in_i_delay <= 0;
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in_q_delay <= 0;
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end else if (enable) begin
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// 1st cycle
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abs_i <= in_i[DATA_WIDTH-1]? ~in_i+1: in_i;
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abs_q <= in_q[DATA_WIDTH-1]? ~in_q+1: in_q;
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in_i_delay <= in_i;
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in_q_delay <= in_q;
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// 2nd cycle
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if (abs_i >= abs_q) begin
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quadrant <= {in_i_delay[DATA_WIDTH-1], in_q_delay[DATA_WIDTH-1], 1'b0};
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max <= abs_i;
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min <= abs_q;
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end else begin
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quadrant <= {in_i_delay[DATA_WIDTH-1], in_q_delay[DATA_WIDTH-1], 1'b1};
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max <= abs_q;
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min <= abs_i;
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end
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case(quadrant_delayed)
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3'b000: phase <= _phase; // [0, PI/4]
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3'b001: phase <= PI_2 - _phase; // [PI/4, PI/2]
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3'b010: phase <= -_phase; // [-PI/4, 0]
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3'b011: phase <= _phase - PI_2; // [-PI/2, -Pi/4]
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3'b100: phase <= PI - _phase; // [3/4PI, PI]
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3'b101: phase <= PI_2 + _phase; // [PI/2, 3/4PI]
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3'b110: phase <= _phase - PI; // [-3/4PI, -PI]
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3'b111: phase <= -PI_2 - _phase; // [-PI/2, -3/4PI]
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endcase
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end
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end
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endmodule
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