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117 lines
3.2 KiB
Verilog
117 lines
3.2 KiB
Verilog
`include "common_defs.v"
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module demodulate (
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input clock,
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input enable,
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input reset,
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input [7:0] rate,
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input [15:0] cons_i,
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input [15:0] cons_q,
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input input_strobe,
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output reg [5:0] bits,
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output output_strobe
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);
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localparam MAX = 1<<`CONS_SCALE_SHIFT;
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localparam QAM_16_DIV = MAX*2/3;
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localparam QAM_64_DIV_0 = MAX*2/7;
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localparam QAM_64_DIV_1 = MAX*4/7;
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localparam QAM_64_DIV_2 = MAX*6/7;
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localparam BPSK = 1;
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localparam QPSK = 2;
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localparam QAM_16 = 3;
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localparam QAM_64 = 4;
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reg [15:0] cons_i_delayed;
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reg [15:0] cons_q_delayed;
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reg [15:0] abs_cons_i;
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reg [15:0] abs_cons_q;
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reg [2:0] mod;
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delayT #(.DATA_WIDTH(1), .DELAY(2)) stb_delay_inst (
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.clock(clock),
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.reset(reset),
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.data_in(input_strobe),
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.data_out(output_strobe)
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);
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always @(posedge clock) begin
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if (reset) begin
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bits <= 0;
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abs_cons_i <= 0;
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abs_cons_q <= 0;
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cons_i_delayed <= 0;
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cons_q_delayed <= 0;
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mod <= 0;
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end else if (enable) begin
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abs_cons_i <= cons_i[15]? ~cons_i+1: cons_i;
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abs_cons_q <= cons_q[15]? ~cons_q+1: cons_q;
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cons_i_delayed <= cons_i;
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cons_q_delayed <= cons_q;
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case({rate[7], rate[3:0]})
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// 802.11a rates
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5'b01011: begin mod <= BPSK; end
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5'b01111: begin mod <= BPSK; end
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5'b01010: begin mod <= QPSK; end
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5'b01110: begin mod <= QPSK; end
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5'b01001: begin mod <= QAM_16; end
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5'b01101: begin mod <= QAM_16; end
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5'b01000: begin mod <= QAM_64; end
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5'b01100: begin mod <= QAM_64; end
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// 802.11n rates
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5'b10000: begin mod <= BPSK; end
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5'b10001: begin mod <= QPSK; end
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5'b10010: begin mod <= QPSK; end
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5'b10011: begin mod <= QAM_16; end
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5'b10100: begin mod <= QAM_16; end
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5'b10101: begin mod <= QAM_64; end
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5'b10110: begin mod <= QAM_64; end
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5'b10111: begin mod <= QAM_64; end
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default: begin mod <= BPSK; end
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endcase
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case(mod)
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BPSK: begin
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bits[0] <= ~cons_i_delayed[15];
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bits[5:1] <= 0;
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end
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QPSK: begin
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bits[0] <= ~cons_i_delayed[15];
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bits[1] <= ~cons_q_delayed[15];
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bits[5:2] <= 0;
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end
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QAM_16: begin
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bits[0] <= ~cons_i_delayed[15];
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bits[1] <= abs_cons_i < QAM_16_DIV? 1: 0;
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bits[2] <= ~cons_q_delayed[15];
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bits[3] <= abs_cons_q < QAM_16_DIV? 1: 0;
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bits[5:4] <= 0;
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end
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QAM_64: begin
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bits[0] <= ~cons_i_delayed[15];
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bits[1] <= abs_cons_i < QAM_64_DIV_1? 1: 0;
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bits[2] <= abs_cons_i > QAM_64_DIV_0 &&
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abs_cons_i < QAM_64_DIV_2? 1: 0;
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bits[3] <= ~cons_q_delayed[15];
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bits[4] <= abs_cons_q < QAM_64_DIV_1? 1: 0;
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bits[5] <= abs_cons_q > QAM_64_DIV_0 &&
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abs_cons_q < QAM_64_DIV_2? 1: 0;
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end
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endcase
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end
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end
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endmodule
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