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25 lines
364 B
Verilog
25 lines
364 B
Verilog
module deinter_lut
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#(
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parameter DWIDTH = 22,
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parameter AWIDTH = 11
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)
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(
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input clka,
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input [AWIDTH-1:0] addra,
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output reg [DWIDTH-1:0] douta
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);
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reg [DWIDTH-1:0] ram [0:(1<<AWIDTH)-1];
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initial begin
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$readmemb("./deinter_lut.mif", ram);
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end
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always @(posedge clka) begin
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if (ena) begin
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douta <= ram[addra];
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end
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end
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endmodule
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