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68 lines
2.4 KiB
Verilog
68 lines
2.4 KiB
Verilog
/********************************************************
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* An interface to assemble bytes into 64 bits. *
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* *
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* Author: Wei Liu *
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********************************************************/
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module intf_64bit (
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input clock,
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input reset,
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input enable,
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input wire [15:0] pkt_len,
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input wire [31:0] byte_index,
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input wire [7:0] byte_in,
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input wire byte_strobe,
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output reg [63:0] data_out,
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output reg output_strobe
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);
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reg byte_strobe_delay ;
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reg [63:0] dout ;
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always @ (posedge clock)
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begin
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byte_strobe_delay <= byte_strobe ;
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//data_out <= dout ;
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end
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always @ (posedge clock)
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begin
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if(reset) begin
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dout <= 64'h0 ;
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data_out <= 64'h0;
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output_strobe <= 1'b0 ;
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end
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else if(enable) begin
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output_strobe <= 1'b0 ;
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data_out <= dout ;
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if(byte_strobe) begin
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dout <= {byte_in, dout[63:8]} ;
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end
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if(byte_strobe_delay) begin
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if(byte_index[2:0] == 3'b0 && byte_index[31:3] > 0 )
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output_strobe <= 1'b1 ;
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else if (pkt_len == byte_index) begin
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output_strobe <= 1'b1 ;
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case (pkt_len[2:0])
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3'b000: data_out <= dout;
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3'b001: begin data_out <= {56'b0,dout[63:56]}; dout <= {56'b0,dout[63:56]}; end
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3'b010: begin data_out <= {48'b0,dout[63:48]}; dout <= {48'b0,dout[63:48]}; end
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3'b011: begin data_out <= {40'b0,dout[63:40]}; dout <= {40'b0,dout[63:40]}; end
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3'b100: begin data_out <= {32'b0,dout[63:32]}; dout <= {32'b0,dout[63:32]}; end
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3'b101: begin data_out <= {24'b0,dout[63:24]}; dout <= {24'b0,dout[63:24]}; end
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3'b110: begin data_out <= {16'b0,dout[63:16]}; dout <= {16'b0,dout[63:16]}; end
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3'b111: begin data_out <= {8'b0,dout[63:8]}; dout <= {8'b0,dout[63:8]}; end
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default: data_out <= dout;
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endcase
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end
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end
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end
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end
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endmodule
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