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68 lines
1.5 KiB
Verilog
68 lines
1.5 KiB
Verilog
// translate rate to idx
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// rate format
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// MSB = 0 --> 802.11a rates, rate[3:0] is the rate bits
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// MSB = 1 --> 802.11n MCS, rate[6:0] is the MCS
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module rate_to_idx
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(
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input clock,
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input enable,
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input reset,
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input [7:0] rate,
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input input_strobe,
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output reg [7:0] idx,
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output reg output_strobe
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);
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always @(posedge clock) begin
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if (reset) begin
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idx <= 0;
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output_strobe <= 0;
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end else if (enable & input_strobe) begin
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case ({rate[7], rate[2:0]})
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4'b0011: begin
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// 6 mbps
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idx <= 0;
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end
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4'b0111: begin
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// 9 mbps
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idx <= 1;
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end
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4'b0010: begin
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// 12 mbps
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idx <= 2;
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end
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4'b0110: begin
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// 18 mbps
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idx <= 3;
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end
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4'b0001: begin
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// 24 mbps
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idx <= 4;
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end
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4'b0101: begin
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// 36 mbps
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idx <= 5;
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end
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4'b0000: begin
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// 48 mbps
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idx <= 6;
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end
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4'b0100: begin
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// 54 mbps
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idx <= 7;
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end
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default: begin
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// mcs
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idx <= {5'b0, rate[2:0]};
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end
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endcase
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output_strobe <= 1;
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end else begin
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output_strobe <= 0;
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end
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end
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endmodule
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