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99 lines
2.8 KiB
Verilog
99 lines
2.8 KiB
Verilog
module power_trigger
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(
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input clock,
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input enable,
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input reset,
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input set_stb,
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input [7:0] set_addr,
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input [31:0] set_data,
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input [31:0] sample_in,
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input sample_in_strobe,
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output reg trigger
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);
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`include "common_params.v"
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localparam S_SKIP = 0;
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localparam S_IDLE = 1;
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localparam S_PACKET = 2;
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reg [1:0] state;
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wire [15:0] power_thres;
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wire [15:0] window_size;
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wire [31:0] num_sample_to_skip;
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wire num_sample_changed;
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reg [31:0] sample_count;
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wire [15:0] input_i = sample_in[31:16];
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reg [15:0] abs_i;
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// threshold to claim a power trigger.
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setting_reg #(.my_addr(SR_POWER_THRES), .width(16), .at_reset(100)) sr_0 (
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.clk(clock), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
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.out(power_thres), .changed());
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// power trigger window
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setting_reg #(.my_addr(SR_POWER_WINDOW), .width(16), .at_reset(80)) sr_1 (
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.clk(clock), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
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.out(window_size), .changed());
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// num samples to skip initially
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setting_reg #(.my_addr(SR_SKIP_SAMPLE), .width(32), .at_reset(5000000)) sr_2 (
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.clk(clock), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
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.out(num_sample_to_skip), .changed(num_sample_changed));
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always @(posedge clock) begin
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if (reset) begin
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sample_count <= 0;
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trigger <= 0;
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abs_i <= 0;
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state <= S_SKIP;
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end else if (enable & sample_in_strobe) begin
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abs_i <= input_i[15]? ~input_i+1: input_i;
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case(state)
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S_SKIP: begin
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if(sample_count > num_sample_to_skip) begin
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state <= S_IDLE;
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end else begin
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sample_count <= sample_count + 1;
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end
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end
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S_IDLE: begin
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if (num_sample_changed) begin
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sample_count <= 0;
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state <= S_SKIP;
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end else if (abs_i > power_thres) begin
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// trigger on any significant signal
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trigger <= 1;
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sample_count <= 0;
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state <= S_PACKET;
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end
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end
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S_PACKET: begin
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if (num_sample_changed) begin
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sample_count <= 0;
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state <= S_SKIP;
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end else if (abs_i < power_thres) begin
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// go back to idle for N consecutive low signals
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if (sample_count > window_size) begin
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trigger <= 0;
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state <= S_IDLE;
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end else begin
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sample_count <= sample_count + 1;
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end
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end else begin
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sample_count <= 0;
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end
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end
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endcase
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end
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end
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endmodule
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