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55 lines
1.0 KiB
Verilog
55 lines
1.0 KiB
Verilog
module complex_to_mag
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#(
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parameter DATA_WIDTH = 16
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)
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(
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input clock,
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input enable,
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input reset,
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input signed [DATA_WIDTH-1:0] i,
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input signed [DATA_WIDTH-1:0] q,
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input input_strobe,
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output reg [DATA_WIDTH-1:0] mag,
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output mag_stb
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);
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reg [DATA_WIDTH-1:0] abs_i;
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reg [DATA_WIDTH-1:0] abs_q;
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reg [DATA_WIDTH-1:0] max;
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reg[ DATA_WIDTH-1:0] min;
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delayT #(.DATA_WIDTH(1), .DELAY(3)) stb_delay_inst (
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.clock(clock),
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.reset(reset),
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.data_in(input_strobe),
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.data_out(mag_stb)
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);
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// http://dspguru.com/dsp/tricks/magnitude-estimator
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// alpha = 1, beta = 1/4
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// avg err 0.006
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always @(posedge clock) begin
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if (reset) begin
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mag <= 0;
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abs_i <= 0;
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abs_q <= 0;
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max <= 0;
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min <= 0;
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end else if (enable) begin
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abs_i <= i[DATA_WIDTH-1]? (~i+1): i;
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abs_q <= q[DATA_WIDTH-1]? (~q+1): q;
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max <= abs_i > abs_q? abs_i: abs_q;
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min <= abs_i > abs_q? abs_q: abs_i;
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mag <= max + (min>>2);
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end
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end
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endmodule
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