xilinx.com xci unknown 1.0 deinter_lut 4096 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 OTHER NONE 8192 32 1 OTHER NONE 8192 32 1 100000000 0 0.000 0 12 12 1 4 0 1 9 0 1 2 NONE 0 0 0 ./ 0 0 0 0 0 0 0 0 Estimated Power for IP : 5.891999 mW zynq 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 deinter_lut.mem deinter_lut.mif 0 1 3 0 1 4096 4096 1 1 22 22 0 0 CE CE ALL 0 0 0 0 0 0 0 1 1 4096 4096 WRITE_FIRST WRITE_FIRST 22 22 zynq 4 Memory_Slave AXI4_Full false Minimum_Area false 9 NONE deinter_lut.coe ALL deinter_lut false false false false false false false false false Always_Enabled Always_Enabled Single_Bit_Error_Injection false Native true no_mem_loaded Single_Port_ROM WRITE_FIRST WRITE_FIRST 0 0 BRAM 0 100 100 0 0 0 0 8kx2 false false 1 1 22 22 false false false false 0 false false CE CE SYNC false false false false false false false 4096 22 22 No_ECC false false false Stand_Alone zynq xilinx.com:zc706:part0:1.2 xc7z045 ffg900 VERILOG MIXED -2 TRUE TRUE IP_Flow 2 TRUE . . 2018.3 OUT_OF_CONTEXT