xilinx.com xci unknown 1.0 rot_lut 4096 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 OTHER NONE 8192 32 1 OTHER NONE 8192 32 1 100000000 0 0.000 0 9 9 1 4 0 1 9 1 0 1 NONE 0 0 0 ./ 0 0 0 0 0 0 0 0 Estimated Power for IP : 3.83175 mW zynquplus 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rot_lut.mem rot_lut.mif 0 1 4 0 1 512 512 1 1 32 32 0 0 CE CE ALL 0 0 0 0 0 0 0 1 1 512 512 WRITE_FIRST WRITE_FIRST 32 32 zynquplus 4 Memory_Slave AXI4_Full false Minimum_Area true 9 NONE rot_lut.coe ALL rot_lut false false false false false false false false false Always_Enabled Always_Enabled Single_Bit_Error_Injection false Native true no_mem_loaded Dual_Port_ROM WRITE_FIRST WRITE_FIRST 0 0 BRAM 0 100 100 0 100 100 0 8kx2 false false 1 1 32 32 false false false false 0 false false CE CE SYNC false false false false false false false 512 32 32 No_ECC false false false Stand_Alone zynquplus xilinx.com:zcu102:part0:3.1 xczu9eg ffvb1156 VERILOG MIXED -2 E TRUE TRUE IP_Flow 2 TRUE . . 2018.3 OUT_OF_CONTEXT