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-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component complex_multiplier
	port (
	ar: IN std_logic_VECTOR(15 downto 0);
	ai: IN std_logic_VECTOR(15 downto 0);
	br: IN std_logic_VECTOR(15 downto 0);
	bi: IN std_logic_VECTOR(15 downto 0);
	clk: IN std_logic;
	pr: OUT std_logic_VECTOR(31 downto 0);
	pi: OUT std_logic_VECTOR(31 downto 0));
end component;

-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of complex_multiplier: component is true;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : complex_multiplier
		port map (
			ar => ar,
			ai => ai,
			br => br,
			bi => bi,
			clk => clk,
			pr => pr,
			pi => pi);
-- INST_TAG_END ------ End INSTANTIATION Template ------------

-- You must compile the wrapper file complex_multiplier.vhd when simulating
-- the core, complex_multiplier. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".