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// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
xfft_v7_1 YourInstanceName (
	.clk(clk),
	.start(start),
	.xn_re(xn_re), // Bus [15 : 0] 
	.xn_im(xn_im), // Bus [15 : 0] 
	.fwd_inv(fwd_inv),
	.fwd_inv_we(fwd_inv_we),
	.rfd(rfd),
	.xn_index(xn_index), // Bus [5 : 0] 
	.busy(busy),
	.edone(edone),
	.done(done),
	.dv(dv),
	.xk_index(xk_index), // Bus [5 : 0] 
	.xk_re(xk_re), // Bus [22 : 0] 
	.xk_im(xk_im)); // Bus [22 : 0] 

// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file xfft_v7_1.v when simulating
// the core, xfft_v7_1. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".