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// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
viterbi_v7_0 YourInstanceName (
	.data_in0(data_in0), // Bus [2 : 0] 
	.data_in1(data_in1), // Bus [2 : 0] 
	.erase(erase), // Bus [1 : 0] 
	.data_out(data_out),
	.rdy(rdy),
	.ce(ce),
	.sclr(sclr),
	.clk(clk));

// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file viterbi_v7_0.v when simulating
// the core, viterbi_v7_0. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".