Add git rev tracking to reg 31

get_git_rev.sh

@@ -0,0 +1,11 @@
+#!/bin/bash
+
+# xianjun.jiao@imec.be
+
+if git log -1 > /dev/null 2>&1; then
+	GIT_REV=$(git log -1 --pretty=%h)
+else
+	GIT_REV=ffffffff
+fi
+
+echo $GIT_REV

openofdm_rx.tcl

@@ -16,6 +16,13 @@
 #
 #*****************************************************************************************
 
+# -----------generate openofdm_rx_git_rev.v---------------
+set  fd  [open  "./verilog/openofdm_rx_git_rev.v"  w]
+set HASHCODE [exec ./get_git_rev.sh]
+puts $fd "`define OPENOFDM_RX_GIT_REV (32'h$HASHCODE)"
+close $fd
+# ----end of generate openofdm_rx_git_rev.v---------------
+
 # Set the reference directory for source file relative paths (by default the value is script directory path)
 set origin_dir [file dirname [info script]]
 
@@ -26,6 +33,7 @@ if { [info exists ::origin_dir_loc] } {
 
 # Set the project name
 set project_name "openofdm_rx"
+exec rm -rf $project_name
 
 # Use project name variable, if specified in the tcl shell
 if { [info exists ::user_project_name] } {

openofdm_rx_side_ch_sim_ultra_scale.tcl

@@ -13,6 +13,13 @@
 #
 #*****************************************************************************************
 
+# -----------generate openofdm_rx_git_rev.v---------------
+set  fd  [open  "./verilog/openofdm_rx_git_rev.v"  w]
+set HASHCODE [exec ./get_git_rev.sh]
+puts $fd "`define OPENOFDM_RX_GIT_REV (32'h$HASHCODE)"
+close $fd
+# ----end of generate openofdm_rx_git_rev.v---------------
+
 # Set the reference directory for source file relative paths (by default the value is script directory path)
 set origin_dir [file dirname [info script]]
 
@@ -23,6 +30,7 @@ if { [info exists ::origin_dir_loc] } {
 
 # Set the project name
 set project_name "openofdm_rx_side_ch_sim_ultra_scale"
+exec rm -rf $project_name
 
 # Use project name variable, if specified in the tcl shell
 if { [info exists ::user_project_name] } {

openofdm_rx_ultra_scale.tcl

@@ -13,6 +13,13 @@
 #
 #*****************************************************************************************
 
+# -----------generate openofdm_rx_git_rev.v---------------
+set  fd  [open  "./verilog/openofdm_rx_git_rev.v"  w]
+set HASHCODE [exec ./get_git_rev.sh]
+puts $fd "`define OPENOFDM_RX_GIT_REV (32'h$HASHCODE)"
+close $fd
+# ----end of generate openofdm_rx_git_rev.v---------------
+
 # Set the reference directory for source file relative paths (by default the value is script directory path)
 set origin_dir [file dirname [info script]]
 
@@ -23,6 +30,7 @@ if { [info exists ::origin_dir_loc] } {
 
 # Set the project name
 set project_name "openofdm_rx_ultra_scale"
+exec rm -rf $project_name
 
 # Use project name variable, if specified in the tcl shell
 if { [info exists ::user_project_name] } {

verilog/openofdm_rx.v

@@ -1,5 +1,7 @@
+// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be;
 
 `timescale 1 ns / 1 ps
+`include "openofdm_rx_git_rev.v"
 
 	module openofdm_rx #
 	(
@@ -101,8 +103,10 @@
     wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg28; 
     wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg29; 
     wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg30; 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg31; 
 	*/
+    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg31; 
+
+	assign slv_reg31 = `OPENOFDM_RX_GIT_REV;
 
 	dot11 # ( 
 	) dot11_i (
@@ -268,8 +272,8 @@
         .SLV_REG27(slv_reg27),
         .SLV_REG28(slv_reg28),
         .SLV_REG29(slv_reg29),
-        .SLV_REG30(slv_reg30),
+        .SLV_REG30(slv_reg30),*/
-        .SLV_REG31(slv_reg31)*/
+        .SLV_REG31(slv_reg31)
 	);
 	
 	endmodule

verilog/openofdm_rx_s_axi.v

@@ -1,3 +1,5 @@
+// based on Xilinx module template
+// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be;
 
 `timescale 1 ns / 1 ps
 
@@ -45,8 +47,8 @@
         input  wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG27,
         input  wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG28,
         input  wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG29,
-        input  wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG30,
+        input  wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG30,*/
-        input  wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG31,*/
+        input  wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG31,
 		// User ports ends
 		// Do not modify the ports beyond this line
 
@@ -165,8 +167,8 @@
 	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg27;
 	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg28;
 	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg29;
-	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg30;
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg30;*/
-	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg31;*/
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg31;
 	wire	 slv_reg_rden;
 	wire	 slv_reg_wren;
 	reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;
@@ -712,8 +714,8 @@
 	        5'h1B   : reg_data_out <= slv_reg27;
 	        5'h1C   : reg_data_out <= slv_reg28;
 	        5'h1D   : reg_data_out <= slv_reg29;
-	        5'h1E   : reg_data_out <= slv_reg30;
+	        5'h1E   : reg_data_out <= slv_reg30;*/
-	        5'h1F   : reg_data_out <= slv_reg31;*/
+	        5'h1F   : reg_data_out <= slv_reg31;
 	        default : reg_data_out <= 0;
 	      endcase
 	end
@@ -752,8 +754,8 @@
           slv_reg27 <= 32'h0;
           slv_reg28 <= 32'h0;
           slv_reg29 <= 32'h0;
-          slv_reg30 <= 32'h0;
+          slv_reg30 <= 32'h0;*/
-          slv_reg31 <= 32'h0;*/
+          slv_reg31 <= 32'h0;
         end 
       else
         begin    
@@ -767,8 +769,8 @@
           slv_reg27 <= SLV_REG27;
           slv_reg28 <= SLV_REG28;
           slv_reg29 <= SLV_REG29;
-          slv_reg30 <= SLV_REG30;
+          slv_reg30 <= SLV_REG30;*/
-          slv_reg31 <= SLV_REG31;*/
+          slv_reg31 <= SLV_REG31;
         end 
     end