diff --git a/verilog/dot11.v b/verilog/dot11.v index ee85f2c..78a8101 100644 --- a/verilog/dot11.v +++ b/verilog/dot11.v @@ -54,7 +54,7 @@ module dot11 ( // sync short output short_preamble_detected, - output [31:0] phase_offset, + output [15:0] phase_offset, // sync long output [31:0] sync_long_metric, @@ -164,13 +164,13 @@ rot_lut rot_lut_inst ( wire [31:0] sync_short_phase_in_i; wire [31:0] sync_short_phase_in_q; wire sync_short_phase_in_stb; -wire [31:0] sync_short_phase_out; +wire [15:0] sync_short_phase_out; wire sync_short_phase_out_stb; wire [31:0] eq_phase_in_i; wire [31:0] eq_phase_in_q; wire eq_phase_in_stb; -wire [31:0] eq_phase_out; +wire [15:0] eq_phase_out; wire eq_phase_out_stb; wire[31:0] phase_in_i = state == S_SYNC_SHORT? @@ -180,7 +180,7 @@ wire[31:0] phase_in_q = state == S_SYNC_SHORT? wire phase_in_stb = state == S_SYNC_SHORT? sync_short_phase_in_stb: eq_phase_in_stb; -wire [31:0] phase_out; +wire [15:0] phase_out; wire phase_out_stb; assign sync_short_phase_out = phase_out; diff --git a/verilog/equalizer.v b/verilog/equalizer.v index c499835..f68b723 100644 --- a/verilog/equalizer.v +++ b/verilog/equalizer.v @@ -15,7 +15,7 @@ module equalizer output [31:0] phase_in_i, output [31:0] phase_in_q, output reg phase_in_stb, - input [31:0] phase_out, + input [15:0] phase_out, input phase_out_stb, output [`ROTATE_LUT_LEN_SHIFT-1:0] rot_addr, @@ -119,7 +119,7 @@ reg signed [31:0] pilot_sum_q; assign phase_in_i = pilot_sum_i; assign phase_in_q = pilot_sum_q; -reg signed [31:0] pilot_phase; +reg signed [15:0] pilot_phase; reg rot_in_stb; wire signed [15:0] rot_i; @@ -188,7 +188,8 @@ wire signed [15:0] norm_i_signed, norm_q_signed; assign norm_i_signed = sample_out[31:16]; assign norm_q_signed = sample_out[15:0]; -wire signed [31:0] prod_i_signed, prod_q_signed, prod_i_scaled_signed, prod_q_scaled_signed, phase_out_signed; +wire signed [31:0] prod_i_signed, prod_q_signed, prod_i_scaled_signed, prod_q_scaled_signed; +wire signed [15:0] phase_out_signed; assign prod_i_signed = prod_i; assign prod_q_signed = prod_q; assign prod_i_scaled_signed = prod_i_scaled; diff --git a/verilog/phase.v b/verilog/phase.v index 4a1a2e3..18c79fe 100644 --- a/verilog/phase.v +++ b/verilog/phase.v @@ -14,7 +14,7 @@ module phase input input_strobe, // [-pi, pi) scaled up by 512 - output reg signed [31:0] phase, + output reg signed [15:0] phase, output output_strobe ); `include "common_params.v" diff --git a/verilog/rotate.v b/verilog/rotate.v index e5da2bb..d618d77 100644 --- a/verilog/rotate.v +++ b/verilog/rotate.v @@ -10,7 +10,7 @@ module rotate input [15:0] in_q, // [-PI, PI] // scaled up by ATAN_LUT_SCALE_SHIFT - input signed [31:0] phase, + input signed [15:0] phase, input input_strobe, output [`ROTATE_LUT_LEN_SHIFT-1:0] rot_addr, @@ -22,15 +22,15 @@ module rotate ); `include "common_params.v" -reg [31:0] phase_delayed; -reg [31:0] phase_abs; +reg [15:0] phase_delayed; +reg [15:0] phase_abs; reg [2:0] quadrant; reg [2:0] quadrant_delayed; wire [15:0] in_i_delayed; wire [15:0] in_q_delayed; -reg [31:0] actual_phase; +reg [15:0] actual_phase; wire [15:0] raw_rot_i; wire [15:0] raw_rot_q; @@ -100,21 +100,21 @@ always @(posedge clock) begin `endif // cycle 1 - phase_abs <= phase[31]? ~phase+1: phase; + phase_abs <= phase[15]? ~phase+1: phase; phase_delayed <= phase; // cycle 2 if (phase_abs <= PI_4) begin - quadrant <= {phase_delayed[31], 2'b00}; + quadrant <= {phase_delayed[15], 2'b00}; actual_phase <= phase_abs; end else if (phase_abs <= PI_2) begin - quadrant <= {phase_delayed[31], 2'b01}; + quadrant <= {phase_delayed[15], 2'b01}; actual_phase <= PI_2 - phase_abs; end else if (phase_abs <= PI_3_4) begin - quadrant <= {phase_delayed[31], 2'b10}; + quadrant <= {phase_delayed[15], 2'b10}; actual_phase <= phase_abs - PI_2; end else begin - quadrant <= {phase_delayed[31], 2'b11}; + quadrant <= {phase_delayed[15], 2'b11}; actual_phase <= PI - phase_abs; end diff --git a/verilog/sync_long.v b/verilog/sync_long.v index 21eba80..0959e08 100644 --- a/verilog/sync_long.v +++ b/verilog/sync_long.v @@ -5,7 +5,7 @@ module sync_long ( input [31:0] sample_in, input sample_in_strobe, - input signed [31:0] phase_offset, + input signed [15:0] phase_offset, input short_gi, output [`ROTATE_LUT_LEN_SHIFT-1:0] rot_addr, diff --git a/verilog/sync_short.v b/verilog/sync_short.v index a1ac46d..1e6ba9b 100644 --- a/verilog/sync_short.v +++ b/verilog/sync_short.v @@ -12,14 +12,14 @@ module sync_short ( output reg short_preamble_detected, - input [31:0] phase_out, + input [15:0] phase_out, input phase_out_stb, output [31:0] phase_in_i, output [31:0] phase_in_q, output phase_in_stb, - output reg signed [31:0] phase_offset + output reg signed [15:0] phase_offset ); `include "common_params.v" @@ -52,7 +52,7 @@ wire [31:0] freq_offset_i; wire [31:0] freq_offset_q; wire freq_offset_stb; -reg [31:0] phase_out_neg; +reg [15:0] phase_out_neg; wire [31:0] delay_prod_avg_mag; wire delay_prod_avg_mag_stb; @@ -81,7 +81,8 @@ reg has_neg; // =============save signal to file for matlab bit-true comparison=========== integer file_open_trigger = 0; integer mag_sq_fd, mag_sq_avg_fd, prod_fd, prod_avg_fd, phase_in_fd, phase_out_fd, delay_prod_avg_mag_fd; -wire signed [31:0] prod_i, prod_q, prod_avg_i, prod_avg_q, phase_in_i_signed, phase_in_q_signed, phase_out_signed; +wire signed [31:0] prod_i, prod_q, prod_avg_i, prod_avg_q, phase_in_i_signed, phase_in_q_signed; +wire signed [15:0] phase_out_signed; assign prod_i = prod[63:32]; assign prod_q = prod[31:0]; assign prod_avg_i = prod_avg[63:32]; @@ -285,7 +286,7 @@ always @(posedge clock) begin pos_count <= 0; neg_count <= 0; short_preamble_detected <= has_pos & has_neg; - phase_offset <= {{4{phase_out_neg[31]}}, phase_out_neg[31:4]}; + phase_offset <= {{4{phase_out_neg[15]}}, phase_out_neg[15:4]}; end else begin plateau_count <= plateau_count + 1; short_preamble_detected <= 0;