diff --git a/verilog/dot11.v b/verilog/dot11.v
index 774dbab..fec5f9f 100644
--- a/verilog/dot11.v
+++ b/verilog/dot11.v
@@ -1,8 +1,11 @@
 `include "common_defs.v"
 `include "openofdm_rx_pre_def.v"
 
-// `define DEBUG_PREFIX (*mark_debug="true",DONT_TOUCH="TRUE"*)
+`ifdef OPENOFDM_RX_ENABLE_DBG
+`define DEBUG_PREFIX (*mark_debug="true",DONT_TOUCH="TRUE"*)
+`else
 `define DEBUG_PREFIX
+`endif
 
 module dot11 (
     input clock,
diff --git a/verilog/openofdm_rx.v b/verilog/openofdm_rx.v
index 1c8dad2..b736f45 100644
--- a/verilog/openofdm_rx.v
+++ b/verilog/openofdm_rx.v
@@ -5,6 +5,12 @@
 `timescale 1 ns / 1 ps
 `include "openofdm_rx_git_rev.v"
 
+`ifdef OPENOFDM_RX_ENABLE_DBG
+`define DEBUG_PREFIX (*mark_debug="true",DONT_TOUCH="TRUE"*)
+`else
+`define DEBUG_PREFIX
+`endif
+
 	module openofdm_rx #
 	(
 		parameter integer IQ_DATA_WIDTH	= 16,
@@ -18,7 +24,7 @@
 		//input  wire openofdm_core_rst,
 		input  wire signed [(RSSI_HALF_DB_WIDTH-1):0] rssi_half_db,
 		input  wire [(2*IQ_DATA_WIDTH-1):0] sample_in,
-    	input  wire sample_in_strobe,
+    input  wire sample_in_strobe,
 
 		output wire demod_is_ongoing, // this needs to be corrected further to indicate actual RF on going regardless the latency
 //		output wire pkt_ht,
@@ -40,8 +46,8 @@
 		output wire fcs_out_strobe,
 		output wire fcs_ok,
 		// for side channel
-    	output wire [31:0] csi,
-    	output wire csi_valid,
+    output wire [31:0] csi,
+    output wire csi_valid,
 		output wire signed [31:0] phase_offset_taken,
 		output wire [31:0] equalizer,
 		output wire equalizer_valid,
@@ -77,48 +83,51 @@
 	);
 
 	// reg0~19 for config write; from reg20 for reading status
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg0; 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg1; // 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg2; 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg3; // 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg4; // 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg5; // 
-		/*
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg6; // 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg7; // 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg8; 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg9; // 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg10; 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg11; 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg12; 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg13; 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg14; 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg15; 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg16; 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg17; 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg18; 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg19; */
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg20; // read openofdm rx core internal state
-    /*
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg21; 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg22; 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg23; 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg24; 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg25; 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg26; 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg27; 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg28; 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg29; 
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg30; 
-	*/
-    wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg31; 
-
-	assign slv_reg31 = `OPENOFDM_RX_GIT_REV;
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg0; 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg1; // 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg2; 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg3; // 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg4; // 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg5; // 
+	/*
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg6; // 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg7; // 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg8; 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg9; // 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg10; 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg11; 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg12; 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg13; 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg14; 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg15; 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg16; 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg17; 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg18; 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg19; */
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg20; // read openofdm rx core internal state
+	/*
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg21; 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg22; 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg23; 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg24; 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg25; 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg26; 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg27; 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg28; 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg29; 
+	wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg30; 
+*/
+  wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg31; 
 
+	`DEBUG_PREFIX wire [(RSSI_HALF_DB_WIDTH-1):0] rx_sensitivity_th;
 	wire power_trigger;
 	wire sig_valid = (pkt_header_valid_strobe&pkt_header_valid);
 	wire receiver_rst;
 
+	assign slv_reg31 = `OPENOFDM_RX_GIT_REV;
+
+	assign rx_sensitivity_th = slv_reg2[(RSSI_HALF_DB_WIDTH-1):0];
+
 	signal_watchdog signal_watchdog_inst (
 		.clk(s00_axi_aclk),
 		.rstn(s00_axi_aresetn),
@@ -131,10 +140,10 @@
 		.power_trigger(power_trigger|(~slv_reg1[12])),//by default the watchdog will run regardless the power_trigger
 
 		.signal_len(pkt_len),
-    	.sig_valid(sig_valid),
+    .sig_valid(sig_valid),
 
 		.min_signal_len_th(slv_reg4[15:12]),
-    	.max_signal_len_th(slv_reg4[31:16]),
+    .max_signal_len_th(slv_reg4[31:16]),
 		.dc_running_sum_th(slv_reg2[23:16]),
 
 		.receiver_rst(receiver_rst)
@@ -148,7 +157,7 @@
 		.reset ( (~s00_axi_aresetn)|slv_reg0[0]|receiver_rst ),
 		.reset_without_watchdog((~s00_axi_aresetn)|slv_reg0[0]),
 
-		.power_thres(slv_reg2[10:0]),
+		.power_thres(rx_sensitivity_th),
 		.min_plateau(slv_reg3),
 		.threshold_scale(~slv_reg1[8]),
 
@@ -317,3 +326,4 @@
 	);
 	
 	endmodule
+