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Change the device/board to 7020 for low-end device friendly (Avoid the license issue in the default case)

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Jiao Xianjun 2022-05-11 10:30:18 +02:00 committed by GitHub
parent 5d4e72f66e
commit ac1a75e55a
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1 changed files with 2 additions and 2 deletions
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openofdm_rx.tcl
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@ -92,7 +92,7 @@ if { $::argc > 0 } {
set src_dir "[file normalize "$origin_dir/verilog"]" set src_dir "[file normalize "$origin_dir/verilog"]"
# Create project # Create project
create_project ${project_name} ./${project_name} -part xc7z045ffg900-2 create_project ${project_name} ./${project_name} -part xc7z020clg484-1
# Set the directory path for the new project # Set the directory path for the new project
set proj_dir [get_property directory [current_project]] set proj_dir [get_property directory [current_project]]
@ -103,7 +103,7 @@ set proj_dir [get_property directory [current_project]]
# Set project properties # Set project properties
set obj [current_project] set obj [current_project]
set_property -name "board_connections" -value "" -objects $obj set_property -name "board_connections" -value "" -objects $obj
set_property -name "board_part" -value "xilinx.com:zc706:part0:1.2" -objects $obj # set_property -name "board_part" -value "xilinx.com:zc706:part0:1.2" -objects $obj
set_property -name "compxlib.activehdl_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/activehdl" -objects $obj set_property -name "compxlib.activehdl_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/activehdl" -objects $obj
set_property -name "compxlib.funcsim" -value "1" -objects $obj set_property -name "compxlib.funcsim" -value "1" -objects $obj
set_property -name "compxlib.ies_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/ies" -objects $obj set_property -name "compxlib.ies_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/ies" -objects $obj