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HT/non_HT detection requires at most 9 clocks

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mmehari 2022-01-04 22:05:38 +01:00
parent 8bc2d7f0a4
commit aaa8ef3ce5
1 changed files with 1 additions and 1 deletions
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verilog/dot11.v
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@ -394,7 +394,7 @@ equalizer equalizer_inst (
); );
delayT #(.DATA_WIDTH(33), .DELAY(6)) eq_delay_inst ( delayT #(.DATA_WIDTH(33), .DELAY(9)) eq_delay_inst (
.clock(clock), .clock(clock),
.reset(reset), .reset(reset),