diff --git a/openofdm_rx.tcl b/openofdm_rx.tcl
index 70c2643..84dc8e0 100644
--- a/openofdm_rx.tcl
+++ b/openofdm_rx.tcl
@@ -60,6 +60,8 @@ if {$NUM_CLK_PER_US == 100} {
   throw {NUM_CLK_PER_US MUST BE 100/200/240/400!}
 }
 
+puts $fd "`define BETTER_SENSITIVITY"
+
 if {$ARGUMENT3 eq ""} {
   puts $fd "`define SAMPLE_FILE \"../../../../../testing_inputs/simulated/ht_mcs7_gi1_aggr0_len14_pre100_post200_openwifi.txt\""
 } else {
diff --git a/verilog/dot11.v b/verilog/dot11.v
index e4f772b..34f58da 100644
--- a/verilog/dot11.v
+++ b/verilog/dot11.v
@@ -14,6 +14,7 @@ module dot11 (
     // add ports for register based inputs
     input [10:0] power_thres,
     input [31:0] min_plateau,
+    input threshold_scale,
 
     // INPUT: RSSI
     input [10:0] rssi_half_db,
@@ -330,6 +331,8 @@ sync_short sync_short_inst (
     .enable(enable & sync_short_enable),
 
     .min_plateau(min_plateau),
+    .threshold_scale(threshold_scale),
+    
     .sample_in(sample_in),
     .sample_in_strobe(sample_in_strobe),
 
diff --git a/verilog/dot11_tb.v b/verilog/dot11_tb.v
index 64ad445..da84a91 100644
--- a/verilog/dot11_tb.v
+++ b/verilog/dot11_tb.v
@@ -5,6 +5,12 @@
 module dot11_tb;
 `include "common_params.v"
 
+`ifdef BETTER_SENSITIVITY
+`define THRESHOLD_SCALE 1
+`else
+`define THRESHOLD_SCALE 0
+`endif
+
 reg clock;
 reg reset;
 reg enable;
@@ -478,6 +484,7 @@ dot11 dot11_inst (
 
     .power_thres(11'd0),
     .min_plateau(32'd100),
+    .threshold_scale(`THRESHOLD_SCALE),
 
     .rssi_half_db(rssi_half_db),
     .sample_in(sample_in),
diff --git a/verilog/openofdm_rx.v b/verilog/openofdm_rx.v
index 3bd1dd9..c3b8e3f 100644
--- a/verilog/openofdm_rx.v
+++ b/verilog/openofdm_rx.v
@@ -140,6 +140,7 @@
 
 		.power_thres(slv_reg2[10:0]),
 		.min_plateau(slv_reg3),
+		.threshold_scale(slv_reg1[8]),
 
 		.rssi_half_db(rssi_half_db),
 
diff --git a/verilog/sync_short.v b/verilog/sync_short.v
index f3d2c94..1594a3b 100644
--- a/verilog/sync_short.v
+++ b/verilog/sync_short.v
@@ -6,6 +6,7 @@ module sync_short (
     input enable,
 
     input [31:0] min_plateau,
+    input threshold_scale,
 
     input [31:0] sample_in,
     input sample_in_strobe,
@@ -216,7 +217,7 @@ always @(posedge clock) begin
         phase_out_neg <= ~phase_out + 1;
         phase_offset_neg <= {{4{phase_out[15]}}, phase_out[15:4]};
 
-        prod_thres <= {1'b0, mag_sq_avg[31:1]} + {2'b0, mag_sq_avg[31:2]};
+        prod_thres <= ( threshold_scale? ({2'b0, mag_sq_avg[31:2]} + {3'b0, mag_sq_avg[31:3]}):({1'b0, mag_sq_avg[31:1]} + {2'b0, mag_sq_avg[31:2]}) );
         
         if (delay_prod_avg_mag_stb) begin
             if (delay_prod_avg_mag > prod_thres) begin