mirror of
https://github.com/jhshi/openofdm.git
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LVPE correction before estimation
- Add state in equalizer and rename others - Add new dumper files in testbench to check with MATLAB
This commit is contained in:
thavinga
parent
b0df85040f
commit
95e93cadfd
@ -88,6 +88,10 @@ integer phase_offset_pilot_sum_fd;
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integer phase_offset_phase_out_fd;
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integer cpe_fd;
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integer lvpe_fd;
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integer sxy_fd;
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integer prev_peg_fd;
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integer peg_sym_scale_fd;
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integer peg_pilot_scale_fd;
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integer rot_in_fd;
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integer rot_out_fd;
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integer equalizer_prod_fd;
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@ -163,6 +167,10 @@ always @(posedge clock) begin
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phase_offset_phase_out_fd = $fopen("./phase_offset_phase_out.txt", "w");
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cpe_fd = $fopen("./cpe.txt", "w");
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lvpe_fd = $fopen("./lvpe.txt", "w");
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sxy_fd = $fopen("./sxy.txt", "w");
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prev_peg_fd = $fopen("./prev_peg.txt", "w");
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peg_sym_scale_fd = $fopen("./peg_sym_scale.txt", "w");
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peg_pilot_scale_fd = $fopen("./peg_pilot_scale.txt", "w");
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rot_in_fd = $fopen("./rot_in.txt", "w");
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rot_out_fd = $fopen("./rot_out.txt", "w");
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equalizer_prod_fd = $fopen("./equalizer_prod.txt", "w");
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@ -285,6 +293,10 @@ always @(posedge clock) begin
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$fclose(phase_offset_phase_out_fd);
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$fclose(cpe_fd);
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$fclose(lvpe_fd);
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$fclose(sxy_fd);
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$fclose(prev_peg_fd);
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$fclose(peg_sym_scale_fd);
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$fclose(peg_pilot_scale_fd);
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$fclose(rot_in_fd);
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$fclose(rot_out_fd);
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$fclose(equalizer_prod_fd);
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@ -430,25 +442,25 @@ always @(posedge clock) begin
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$fflush(sync_long_out_fd);
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end
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// equalizer
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if ((dot11_inst.equalizer_inst.num_ofdm_sym == 1 || (dot11_inst.equalizer_inst.pkt_ht==1 && dot11_inst.equalizer_inst.num_ofdm_sym==5)) && dot11_inst.equalizer_inst.state == dot11_inst.equalizer_inst.S_CALC_FREQ_OFFSET && dot11_inst.equalizer_inst.sample_in_strobe_dly == 1 && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset) begin
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if ((dot11_inst.equalizer_inst.num_ofdm_sym == 1 || (dot11_inst.equalizer_inst.pkt_ht==1 && dot11_inst.equalizer_inst.num_ofdm_sym==5)) && dot11_inst.equalizer_inst.state == dot11_inst.equalizer_inst.S_CPE_ESTIMATE && dot11_inst.equalizer_inst.sample_in_strobe_dly == 1 && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset) begin
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$fwrite(new_lts_fd, "%d %d %d\n", iq_count, dot11_inst.equalizer_inst.lts_i_out, dot11_inst.equalizer_inst.lts_q_out);
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$fflush(new_lts_fd);
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end
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if (dot11_inst.equalizer_inst.pilot_in_stb && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
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if (dot11_inst.equalizer_inst.pilot_in_stb && dot11_inst.equalizer_inst.enable && dot11_inst.equalizer_inst.state==dot11_inst.equalizer_inst.S_CPE_ESTIMATE && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
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$fwrite(phase_offset_pilot_input_fd, "%d %d %d\n", iq_count, dot11_inst.equalizer_inst.input_i, dot11_inst.equalizer_inst.input_q);
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$fflush(phase_offset_pilot_input_fd);
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$fwrite(phase_offset_lts_input_fd, "%d %d %d\n", iq_count, dot11_inst.equalizer_inst.lts_i_out, dot11_inst.equalizer_inst.lts_q_out);
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$fflush(phase_offset_lts_input_fd);
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end
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if (dot11_inst.equalizer_inst.pilot_out_stb && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
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if (dot11_inst.equalizer_inst.pilot_out_stb && dot11_inst.equalizer_inst.enable && dot11_inst.equalizer_inst.state==dot11_inst.equalizer_inst.S_CPE_ESTIMATE && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
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$fwrite(phase_offset_pilot_fd, "%d %d %d\n", iq_count, dot11_inst.equalizer_inst.pilot_i, dot11_inst.equalizer_inst.pilot_q);
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$fflush(phase_offset_pilot_fd);
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end
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if (dot11_inst.equalizer_inst.phase_in_stb && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
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if (dot11_inst.equalizer_inst.phase_in_stb && dot11_inst.equalizer_inst.enable && dot11_inst.equalizer_inst.state==dot11_inst.equalizer_inst.S_PILOT_PE_CORRECTION && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
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$fwrite(phase_offset_pilot_sum_fd, "%d %d %d\n", iq_count, dot11_inst.equalizer_inst.pilot_sum_i, dot11_inst.equalizer_inst.pilot_sum_q);
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$fflush(phase_offset_pilot_sum_fd);
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end
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if (dot11_inst.equalizer_inst.phase_out_stb && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
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if (dot11_inst.equalizer_inst.phase_out_stb && dot11_inst.equalizer_inst.enable && dot11_inst.equalizer_inst.state==dot11_inst.equalizer_inst.S_PILOT_PE_CORRECTION && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
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$fwrite(phase_offset_phase_out_fd, "%d %d\n", iq_count, $signed(dot11_inst.equalizer_inst.phase_out));
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$fflush(phase_offset_phase_out_fd);
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end
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@ -460,13 +472,29 @@ always @(posedge clock) begin
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$fwrite(lvpe_fd, "%d %d\n", iq_count, $signed(dot11_inst.equalizer_inst.lvpe));
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$fflush(lvpe_fd);
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end
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if (dot11_inst.equalizer_inst.rot_in_stb && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
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if (dot11_inst.equalizer_inst.lvpe_out_stb && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
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$fwrite(sxy_fd, "%d %d\n", iq_count, $signed(dot11_inst.equalizer_inst.Sxy));
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$fflush(sxy_fd);
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end
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if (dot11_inst.equalizer_inst.num_output == dot11_inst.equalizer_inst.num_data_carrier && dot11_inst.equalizer_inst.enable && dot11_inst.equalizer_inst.state==dot11_inst.equalizer_inst.S_ALL_SC_PE_CORRECTION && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
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$fwrite(prev_peg_fd, "%d %d\n", iq_count, $signed(dot11_inst.equalizer_inst.prev_peg_reg));
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$fflush(prev_peg_fd);
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end
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if (dot11_inst.equalizer_inst.lvpe_out_stb && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
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$fwrite(peg_sym_scale_fd, "%d %d\n", iq_count, $signed(dot11_inst.equalizer_inst.peg_sym_scale));
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$fflush(peg_sym_scale_fd);
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end
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if (dot11_inst.equalizer_inst.pilot_count1 < 4 && dot11_inst.equalizer_inst.enable && dot11_inst.equalizer_inst.enable && dot11_inst.equalizer_inst.state==dot11_inst.equalizer_inst.S_PILOT_PE_CORRECTION && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
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$fwrite(peg_pilot_scale_fd, "%d %d\n", iq_count, $signed(dot11_inst.equalizer_inst.peg_pilot_scale));
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$fflush(peg_pilot_scale_fd);
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end
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if (dot11_inst.equalizer_inst.rot_in_stb && dot11_inst.equalizer_inst.enable && dot11_inst.equalizer_inst.state==dot11_inst.equalizer_inst.S_ALL_SC_PE_CORRECTION && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
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$fwrite(rot_in_fd, "%d %d %d %d\n", iq_count, $signed(dot11_inst.equalizer_inst.buf_i_out), $signed(dot11_inst.equalizer_inst.buf_q_out), $signed(dot11_inst.equalizer_inst.sym_phase));
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$fflush(rot_in_fd);
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end
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if (dot11_inst.equalizer_inst.rot_out_stb && dot11_inst.equalizer_inst.state==dot11_inst.equalizer_inst.S_ADJUST_FREQ_and_SAMPL_OFFSET && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
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if (dot11_inst.equalizer_inst.rot_out_stb && dot11_inst.equalizer_inst.state==dot11_inst.equalizer_inst.S_ALL_SC_PE_CORRECTION && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
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// when enable is 0, it locked equalizer all internal variables till the next reset/enable, some large delayed signal, such as rot out, logged with some garbage
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// limite the log to dot11_inst.equalizer_inst.S_ADJUST_FREQ_and_SAMPL_OFFSET state
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// limite the log to dot11_inst.equalizer_inst.S_ALL_SC_PE_CORRECTION state
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$fwrite(rot_out_fd, "%d %d %d\n", iq_count, dot11_inst.equalizer_inst.rot_i, dot11_inst.equalizer_inst.rot_q);
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$fflush(rot_out_fd);
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end
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@ -82,11 +82,31 @@ reg [63:0] ht_lts_ref;
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reg [63:0] subcarrier_mask;
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reg [63:0] data_subcarrier_mask;
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reg [63:0] pilot_mask;
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reg [5:0] pilot_loc[3:0];
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reg signed [5:0] pilot_idx[3:0];
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localparam pilot_loc1 = 7;
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localparam pilot_loc2 = 21;
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localparam pilot_loc3 = 43;
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localparam pilot_loc4 = 57;
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localparam signed pilot_idx1 = 8;
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localparam signed pilot_idx2 = 22;
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localparam signed pilot_idx3 = -20;
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localparam signed pilot_idx4 = -6;
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initial begin
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pilot_loc[0] = pilot_loc1;
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pilot_idx[0] = pilot_idx1;
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pilot_loc[1] = pilot_loc2;
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pilot_idx[1] = pilot_idx2;
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pilot_loc[2] = pilot_loc3;
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pilot_idx[2] = pilot_idx3;
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pilot_loc[3] = pilot_loc4;
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pilot_idx[3] = pilot_idx4;
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end
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reg [126:0] polarity;
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reg [3:0] ht_polarity;
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reg [3:0] current_polarity;
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reg [3:0] pilot_count1, pilot_count2;
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reg [3:0] pilot_count1, pilot_count2, pilot_count3;
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reg signed [15:0] input_i;
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reg signed [15:0] input_q;
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@ -125,8 +145,6 @@ reg signed [31:0] pilot_sum_q;
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assign phase_in_i = pilot_i_reg;
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assign phase_in_q = pilot_q_reg;
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reg sum_phase;
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//reg signed [15:0] pilot_phase_err;
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reg signed [16:0] pilot_phase_err; // 15 --> 16 = 15 + 1, extended from cpe
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reg signed [15:0] cpe; // common phase error due to RFO
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@ -135,14 +153,15 @@ reg signed [23:0] Sxy; // 15-->23. to avoid overflow: pilot_phase_err 16 + 5 + 2
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localparam Sx2 = 980;
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// linear varying phase error (LVPE) parameters
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reg signed [7:0] sym_idx;
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reg signed [7:0] sym_idx, sym_idx2;
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reg lvpe_in_stb;
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wire lvpe_out_stb;
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wire signed [31:0] lvpe_dividend, lvpe;
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wire signed [31:0] lvpe_dividend, lvpe, peg_sym_scale;
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wire signed [23:0] lvpe_divisor;
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assign lvpe_dividend = (sym_idx <= 33 ? sym_idx*Sxy : (sym_idx-64)*Sxy);
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assign lvpe_divisor = Sx2;
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reg signed [31:0] prev_peg, prev_peg_reg, peg_pilot_scale;
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assign peg_sym_scale = (sym_idx2 <= 33 ? sym_idx2*prev_peg : (sym_idx2-64)*prev_peg);
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//reg signed [15:0] phase_err;
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reg signed [17:0] phase_err; // 15-->16: phase_err <= cpe + lvpe[17:0]; 16 + 1 = 17 for sym_phase
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@ -181,11 +200,11 @@ reg signed [18:0] lts_sum_q;
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reg [2:0] lts_mv_avg_len;
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reg lts_div_in_stb;
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wire [31:0] dividend_i = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? (lts_sum_i[18] == 0 ? {13'h0,lts_sum_i} : {13'h1FFF,lts_sum_i}) : (state == S_ADJUST_FREQ_and_SAMPL_OFFSET ? prod_i_scaled : 0);
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wire [31:0] dividend_q = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? (lts_sum_q[18] == 0 ? {13'h0,lts_sum_q} : {13'h1FFF,lts_sum_q}) : (state == S_ADJUST_FREQ_and_SAMPL_OFFSET ? prod_q_scaled : 0);
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wire [23:0] divisor_i = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? {21'b0,lts_mv_avg_len} : (state == S_ADJUST_FREQ_and_SAMPL_OFFSET ? mag_sq[23:0] : 1);
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wire [23:0] divisor_q = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? {21'b0,lts_mv_avg_len} : (state == S_ADJUST_FREQ_and_SAMPL_OFFSET ? mag_sq[23:0] : 1);
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wire div_in_stb = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? lts_div_in_stb : (state == S_ADJUST_FREQ_and_SAMPL_OFFSET ? prod_out_strobe : 0);
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wire [31:0] dividend_i = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? (lts_sum_i[18] == 0 ? {13'h0,lts_sum_i} : {13'h1FFF,lts_sum_i}) : (state == S_ALL_SC_PE_CORRECTION ? prod_i_scaled : 0);
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wire [31:0] dividend_q = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? (lts_sum_q[18] == 0 ? {13'h0,lts_sum_q} : {13'h1FFF,lts_sum_q}) : (state == S_ALL_SC_PE_CORRECTION ? prod_q_scaled : 0);
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wire [23:0] divisor_i = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? {21'b0,lts_mv_avg_len} : (state == S_ALL_SC_PE_CORRECTION ? mag_sq[23:0] : 1);
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wire [23:0] divisor_q = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? {21'b0,lts_mv_avg_len} : (state == S_ALL_SC_PE_CORRECTION ? mag_sq[23:0] : 1);
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wire div_in_stb = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? lts_div_in_stb : (state == S_ALL_SC_PE_CORRECTION ? prod_out_strobe : 0);
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reg [15:0] num_output;
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@ -206,7 +225,7 @@ wire prod_out_strobe;
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// for side channel
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reg sample_in_strobe_dly;
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assign csi = {lts_i_out, lts_q_out};
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assign csi_valid = ( (num_ofdm_sym == 1 || (pkt_ht==1 && num_ofdm_sym==5)) && state == S_CALC_FREQ_OFFSET && sample_in_strobe_dly == 1 && enable && (~reset) );
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assign csi_valid = ( (num_ofdm_sym == 1 || (pkt_ht==1 && num_ofdm_sym==5)) && state == S_CPE_ESTIMATE && sample_in_strobe_dly == 1 && enable && (~reset) );
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always @(posedge clock) begin
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if (reset) begin
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@ -376,10 +395,11 @@ localparam S_SECOND_LTS = 1;
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localparam S_SMOOTH_CH_DC = 2;
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localparam S_SMOOTH_CH_LTS = 3;
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localparam S_GET_POLARITY = 4;
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localparam S_CALC_FREQ_OFFSET = 5;
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localparam S_CALC_SAMPL_OFFSET = 6;
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localparam S_ADJUST_FREQ_and_SAMPL_OFFSET = 7;
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localparam S_HT_LTS = 8;
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localparam S_CPE_ESTIMATE = 5;
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localparam S_PILOT_PE_CORRECTION = 6;
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localparam S_LVPE_ESTIMATE = 7;
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localparam S_ALL_SC_PE_CORRECTION = 8;
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localparam S_HT_LTS = 9;
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always @(posedge clock) begin
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if (reset|reset_internal) begin
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@ -408,10 +428,12 @@ always @(posedge clock) begin
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current_polarity <= 0;
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pilot_count1 <= 0;
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pilot_count2 <= 0;
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pilot_count3 <= 0;
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in_waddr <= 0;
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in_raddr <= 0;
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sym_idx <= 0;
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sym_idx2 <= 0;
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lts_reg1_i <= 0; lts_reg2_i <= 0; lts_reg3_i <= 0; lts_reg4_i <= 0; lts_reg5_i <= 0;
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lts_reg1_q <= 0; lts_reg2_q <= 0; lts_reg3_q <= 0; lts_reg4_q <= 0; lts_reg5_q <= 0;
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@ -432,7 +454,9 @@ always @(posedge clock) begin
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pilot_i_reg <= 0;
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pilot_q_reg <= 0;
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pilot_iq_phase[0] <= 0; pilot_iq_phase[1] <= 0; pilot_iq_phase[2] <= 0; pilot_iq_phase[3] <= 0;
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sum_phase <= 0;
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prev_peg <= 0;
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prev_peg_reg <= 0;
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peg_pilot_scale <= 0;
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prod_in_strobe <= 0;
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@ -606,10 +630,10 @@ always @(posedge clock) begin
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input_q <= 0;
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lts_raddr <= 0;
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num_ofdm_sym <= num_ofdm_sym + 1;
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state <= S_CALC_FREQ_OFFSET;
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state <= S_CPE_ESTIMATE;
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end
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S_CALC_FREQ_OFFSET: begin
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S_CPE_ESTIMATE: begin
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if (~ht & ht_next) begin
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ht <= 1;
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num_data_carrier <= 52;
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@ -631,10 +655,8 @@ always @(posedge clock) begin
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pilot_mask <= {pilot_mask[0], pilot_mask[63:1]};
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if (pilot_mask[0]) begin
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pilot_count1 <= pilot_count1 + 1;
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current_polarity <= {current_polarity[0],
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current_polarity[3:1]};
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// obtain the conjugate of current pilot sub carrier
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if (current_polarity[0] == 0) begin
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if (current_polarity[pilot_count1] == 0) begin
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input_i <= sample_in[31:16];
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input_q <= ~sample_in[15:0] + 1;
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end else begin
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@ -652,43 +674,92 @@ always @(posedge clock) begin
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if (pilot_out_stb) begin
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pilot_sum_i <= pilot_sum_i + pilot_i;
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pilot_sum_q <= pilot_sum_q + pilot_q;
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pilot_i_reg <= pilot_i;
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pilot_q_reg <= pilot_q;
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phase_in_stb <= 1;
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end else if (pilot_count2 == 4 && sum_phase == 0) begin
|
||||
pilot_count2 <= pilot_count2 + 1;
|
||||
end else if (pilot_count2 == 4) begin
|
||||
pilot_i_reg <= pilot_sum_i;
|
||||
pilot_q_reg <= pilot_sum_q;
|
||||
phase_in_stb <= 1;
|
||||
sum_phase <= 1;
|
||||
pilot_count2 <= 0;
|
||||
end else begin
|
||||
phase_in_stb <= 0;
|
||||
end
|
||||
|
||||
if (phase_out_stb && pilot_count2 < 4) begin
|
||||
pilot_count2 <= pilot_count2 + 1;
|
||||
pilot_iq_phase[pilot_count2] <= phase_out;
|
||||
`ifdef DEBUG_PRINT
|
||||
$display("[PILOT OFFSET] %d", phase_out);
|
||||
`endif
|
||||
end else if (phase_out_stb && pilot_count2 == 4) begin
|
||||
if (phase_out_stb) begin
|
||||
cpe <= phase_out;
|
||||
pilot_count1 <= 0;
|
||||
pilot_count2 <= 0;
|
||||
pilot_count3 <= 0;
|
||||
Sxy <= 0;
|
||||
state <= S_CALC_SAMPL_OFFSET;
|
||||
sum_phase <= 0;
|
||||
in_raddr <= pilot_loc[0][5:0]; // sample in location, compensate for RAM read delay
|
||||
lts_raddr <= pilot_loc[0][5:0]; // LTS location, compensate for RAM read delay
|
||||
peg_pilot_scale <= pilot_idx[0]*prev_peg;
|
||||
state <= S_PILOT_PE_CORRECTION;
|
||||
end
|
||||
end
|
||||
|
||||
S_CALC_SAMPL_OFFSET: begin
|
||||
S_PILOT_PE_CORRECTION: begin
|
||||
// rotate pilots with accumulated PEG up to previous symbol
|
||||
if (pilot_count1 < 4) begin
|
||||
if (pilot_count1 < 3) begin
|
||||
in_raddr <= pilot_loc[pilot_count1+1][5:0];
|
||||
peg_pilot_scale <= (pilot_idx[pilot_count1+1])*prev_peg;
|
||||
rot_in_stb <= 1;
|
||||
end
|
||||
phase_err <= {cpe[15], cpe[15], cpe[15:0]} + peg_pilot_scale[17:0];
|
||||
pilot_count1 <= pilot_count1 + 1;
|
||||
end else begin
|
||||
rot_in_stb <= 0;
|
||||
end
|
||||
|
||||
if (rot_out_stb && pilot_count2 < 4) begin
|
||||
if (pilot_count2 < 3) begin
|
||||
lts_raddr <= pilot_loc[pilot_count2+1][5:0];
|
||||
end
|
||||
// obtain the conjugate of current pilot sub carrier
|
||||
if (current_polarity[pilot_count2] == 0) begin
|
||||
input_i <= rot_i;
|
||||
input_q <= -rot_q;
|
||||
end else begin
|
||||
input_i <= -rot_i;
|
||||
input_q <= rot_q;
|
||||
end
|
||||
pilot_in_stb <= 1; // start complex mult. with LTS pilot
|
||||
pilot_count2 <= pilot_count2 + 1;
|
||||
end else begin
|
||||
pilot_in_stb <= 0;
|
||||
end
|
||||
|
||||
if (pilot_out_stb) begin
|
||||
pilot_i_reg <= pilot_i;
|
||||
pilot_q_reg <= pilot_q;
|
||||
phase_in_stb <= 1;
|
||||
end else begin
|
||||
phase_in_stb <= 0;
|
||||
end
|
||||
|
||||
if (phase_out_stb && pilot_count3 < 4) begin
|
||||
pilot_count3 <= pilot_count3 + 1;
|
||||
pilot_iq_phase[pilot_count3] <= phase_out;
|
||||
end
|
||||
|
||||
if (pilot_count3 == 4) begin
|
||||
phase_in_stb <= 0;
|
||||
pilot_count1 <= 0;
|
||||
pilot_count2 <= 0;
|
||||
pilot_count3 <= 0;
|
||||
state <= S_LVPE_ESTIMATE;
|
||||
end
|
||||
end
|
||||
|
||||
S_LVPE_ESTIMATE: begin
|
||||
if (pilot_count1 < 4) begin
|
||||
// sampling rate offset (SFO) is calculated as pilot phase error
|
||||
if(pilot_iq_phase[pilot_count1] < cpe - 1608) begin
|
||||
pilot_phase_err <= pilot_iq_phase[pilot_count1] - cpe + 3217;
|
||||
end else if(pilot_iq_phase[pilot_count1] > cpe + 1608) begin
|
||||
pilot_phase_err <= pilot_iq_phase[pilot_count1] - cpe - 3217;
|
||||
if(pilot_iq_phase[pilot_count1] < -1608) begin
|
||||
pilot_phase_err <= pilot_iq_phase[pilot_count1] + 3217;
|
||||
end else if(pilot_iq_phase[pilot_count1] > 1608) begin
|
||||
pilot_phase_err <= pilot_iq_phase[pilot_count1] - 3217;
|
||||
end else begin
|
||||
pilot_phase_err <= pilot_iq_phase[pilot_count1] - cpe;
|
||||
pilot_phase_err <= pilot_iq_phase[pilot_count1];
|
||||
end
|
||||
|
||||
pilot_count1 <= pilot_count1 + 1;
|
||||
@ -705,18 +776,19 @@ always @(posedge clock) begin
|
||||
|
||||
in_raddr <= 0;
|
||||
sym_idx <= 0;
|
||||
sym_idx2 <= 1;
|
||||
lvpe_in_stb <= 0;
|
||||
// compensate for RAM read delay
|
||||
lts_raddr <= 1;
|
||||
rot_in_stb <= 0;
|
||||
num_output <= 0;
|
||||
state <= S_ADJUST_FREQ_and_SAMPL_OFFSET;
|
||||
state <= S_ALL_SC_PE_CORRECTION;
|
||||
end
|
||||
// Sx² = ∑(x-x̄)*(x-x̄) = ∑x² = (7² + 21² + (-21)² + (-7)²) = 980
|
||||
// phase error gradient (PEG) = Sxy/Sx²
|
||||
end
|
||||
|
||||
S_ADJUST_FREQ_and_SAMPL_OFFSET: begin
|
||||
S_ALL_SC_PE_CORRECTION: begin
|
||||
if (sym_idx < 64) begin
|
||||
sym_idx <= sym_idx + 1;
|
||||
lvpe_in_stb <= 1;
|
||||
@ -726,10 +798,14 @@ always @(posedge clock) begin
|
||||
|
||||
// first rotate, then normalize by avg LTS
|
||||
if (lvpe_out_stb) begin
|
||||
// phase_err <= cpe + lvpe[15:0];
|
||||
phase_err <= {cpe[15], cpe[15], cpe[15:0]} + lvpe[17:0];
|
||||
sym_idx2 <= sym_idx2 + 1;
|
||||
phase_err <= {cpe[15], cpe[15], cpe[15:0]} + lvpe[17:0] + peg_sym_scale[17:0];
|
||||
rot_in_stb <= 1;
|
||||
in_raddr <= in_raddr + 1;
|
||||
if (sym_idx2 == 32) begin
|
||||
// lvpe output is 32*PEG due to sym_idx
|
||||
prev_peg_reg <= prev_peg_reg + (lvpe >>> 5);
|
||||
end
|
||||
end else begin
|
||||
rot_in_stb <= 0;
|
||||
end
|
||||
@ -754,6 +830,7 @@ always @(posedge clock) begin
|
||||
end
|
||||
|
||||
if (num_output == num_data_carrier) begin
|
||||
prev_peg <= prev_peg_reg;
|
||||
state <= S_GET_POLARITY;
|
||||
end
|
||||
end
|
||||
|
||||
Loading…
Reference in New Issue
Block a user