From 82d2d456e526ff2a383731df3734c6d99f14370e Mon Sep 17 00:00:00 2001 From: mmehari Date: Tue, 4 Jan 2022 22:11:50 +0100 Subject: [PATCH] keep significant bits while performing division during phase calculation --- verilog/phase.v | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/verilog/phase.v b/verilog/phase.v index 18c79fe..6cc0a7e 100644 --- a/verilog/phase.v +++ b/verilog/phase.v @@ -25,6 +25,10 @@ reg [DATA_WIDTH-1:0] abs_i; reg [DATA_WIDTH-1:0] abs_q; reg [DATA_WIDTH-1:0] max; reg [DATA_WIDTH-1:0] min; +wire [DATA_WIDTH-1:0] dividend; +wire [DATA_WIDTH-`ATAN_LUT_LEN_SHIFT-1:0] divisor; +assign dividend = (max > 8388608) ? min : {min[DATA_WIDTH-`ATAN_LUT_LEN_SHIFT-1:0], {`ATAN_LUT_LEN_SHIFT{1'b0}}}; +assign divisor = (max > 8388608) ? max[DATA_WIDTH-1:`ATAN_LUT_LEN_SHIFT] : max[DATA_WIDTH-`ATAN_LUT_LEN_SHIFT-1:0]; wire div_in_stb; @@ -66,8 +70,8 @@ divider div_inst ( .enable(enable), .reset(reset), - .dividend(min), - .divisor({{(`ATAN_LUT_LEN_SHIFT-8){1'b0}}, max[31:`ATAN_LUT_LEN_SHIFT]}), + .dividend(dividend), + .divisor({{(`ATAN_LUT_LEN_SHIFT-8){1'b0}}, divisor}), .input_strobe(div_in_stb), .quotient(quotient),