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remove debug

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This commit is contained in:
Xianjun Jiao 2020-06-12 10:24:59 +02:00
parent abbe9ecde9
commit 6a0073ee58
7 changed files with 56 additions and 56 deletions
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2
verilog/coregen/div_gen_new_ip_core_zynquplus/src/div_gen_div_gen_0_0/div_gen_div_gen_0_0.xci
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@ -112,7 +112,7 @@ e false}}}}}}} TUSER_WIDTH 0}</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.operand_sign">Signed</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.remainder_type">Fractional</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynquplus</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:zcu102:part0:3.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:zcu102:part0:3.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xczu9eg</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffvb1156</spirit:configurableElementValue>

2
verilog/coregen/div_gen_new_ip_core_zynquplus/src/div_gen_xlslice_0_0/div_gen_xlslice_0_0.xci
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@ -18,7 +18,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_WIDTH">56</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynquplus</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:zcu102:part0:3.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:zcu102:part0:3.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xczu9eg</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffvb1156</spirit:configurableElementValue>

2
verilog/deinterleave.v
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@ -164,7 +164,7 @@ localparam S_INPUT = 0;
localparam S_GET_BASE = 1;
localparam S_OUTPUT = 2;
(* mark_debug = "true" *) reg [1:0] state;
reg [1:0] state;
always @(posedge clock) begin
if (reset) begin

48
verilog/dot11.v
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@ -17,34 +17,34 @@ module dot11 (
// INPUT: RSSI
input [10:0] rssi_half_db,
// INPUT: I/Q sample
(* mark_debug = "true" *) input [31:0] sample_in,
(* mark_debug = "true" *) input sample_in_strobe,
(* mark_debug = "true" *) input soft_decoding,
input [31:0] sample_in,
input sample_in_strobe,
input soft_decoding,
// OUTPUT: bytes and FCS status
(* mark_debug = "true" *) output reg demod_is_ongoing,
(* mark_debug = "true" *) output reg pkt_begin,
(* mark_debug = "true" *) output reg pkt_ht,
(* mark_debug = "true" *) output reg pkt_header_valid,
(* mark_debug = "true" *) output reg pkt_header_valid_strobe,
(* mark_debug = "true" *) output reg ht_unsupport,
(* mark_debug = "true" *) output reg [7:0] pkt_rate,
(* mark_debug = "true" *) output reg [15:0] pkt_len,
(* mark_debug = "true" *) output reg [15:0] pkt_len_total,
(* mark_debug = "true" *) output byte_out_strobe,
(* mark_debug = "true" *) output [7:0] byte_out,
(* mark_debug = "true" *) output reg [15:0] byte_count_total,
(* mark_debug = "true" *) output reg [15:0] byte_count,
(* mark_debug = "true" *) output reg fcs_out_strobe,
(* mark_debug = "true" *) output reg fcs_ok,
output reg demod_is_ongoing,
output reg pkt_begin,
output reg pkt_ht,
output reg pkt_header_valid,
output reg pkt_header_valid_strobe,
output reg ht_unsupport,
output reg [7:0] pkt_rate,
output reg [15:0] pkt_len,
output reg [15:0] pkt_len_total,
output byte_out_strobe,
output [7:0] byte_out,
output reg [15:0] byte_count_total,
output reg [15:0] byte_count,
output reg fcs_out_strobe,
output reg fcs_ok,
/////////////////////////////////////////////////////////
// DEBUG PORTS
/////////////////////////////////////////////////////////
// decode status
(* mark_debug = "true" *) output reg [3:0] state,
(* mark_debug = "true" *) output reg [3:0] status_code,
output reg [3:0] state,
output reg [3:0] status_code,
output state_changed,
// power trigger
@ -205,13 +205,13 @@ reg do_descramble;
reg [31:0] num_bits_to_decode;
reg short_gi;
(* mark_debug = "true" *) reg [3:0] old_state;
reg [3:0] old_state;
assign power_trigger = (rssi_half_db>=power_thres? 1: 0);
assign state_changed = state != old_state;
// SIGNAL information
(* mark_debug = "true" *) reg [23:0] signal_bits;
reg [23:0] signal_bits;
assign legacy_rate = signal_bits[3:0];
assign legacy_sig_rsvd = signal_bits[4];
@ -222,8 +222,8 @@ assign legacy_sig_parity_ok = ~^signal_bits[17:0];
// HT-SIG information
(* mark_debug = "true" *) reg [23:0] ht_sig1;
(* mark_debug = "true" *) reg [23:0] ht_sig2;
reg [23:0] ht_sig1;
reg [23:0] ht_sig2;
assign ht_mcs = ht_sig1[6:0];
assign ht_cbw = ht_sig1[7];

2
verilog/equalizer.v
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@ -22,7 +22,7 @@ module equalizer
output reg [31:0] sample_out,
output reg sample_out_strobe,
(* mark_debug = "true" *) output reg [2:0] state
output reg [2:0] state
);

16
verilog/ofdm_decoder.v
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@ -13,17 +13,17 @@ module ofdm_decoder
input do_descramble,
input [31:0] num_bits_to_decode,
(* mark_debug = "false" *) output [5:0] demod_out,
(* mark_debug = "false" *) output demod_out_strobe,
output [5:0] demod_out,
output demod_out_strobe,
(* mark_debug = "false" *) output [7:0] deinterleave_erase_out,
(* mark_debug = "false" *) output deinterleave_erase_out_strobe,
output [7:0] deinterleave_erase_out,
output deinterleave_erase_out_strobe,
(* mark_debug = "false" *) output conv_decoder_out,
(* mark_debug = "false" *) output conv_decoder_out_stb,
output conv_decoder_out,
output conv_decoder_out_stb,
(* mark_debug = "false" *) output descramble_out,
(* mark_debug = "false" *) output descramble_out_strobe,
output descramble_out,
output descramble_out_strobe,
output [7:0] byte_out,
output byte_out_strobe

40
verilog/sync_long.v
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@ -18,7 +18,7 @@ module sync_long (
output reg [31:0] sample_out,
output reg sample_out_strobe,
(* mark_debug = "true" *) output reg [2:0] state
output reg [2:0] state
);
`include "common_params.v"
@ -127,16 +127,16 @@ localparam S_FFT = 4;
reg fft_start;
//wire fft_start_delayed;
(* mark_debug = "false" *) wire fft_in_stb;
(* mark_debug = "false" *) reg fft_loading;
(* mark_debug = "false" *) wire signed [15:0] fft_in_re;
(* mark_debug = "false" *) wire signed [15:0] fft_in_im;
(* mark_debug = "false" *) wire [22:0] fft_out_re;
(* mark_debug = "false" *) wire [22:0] fft_out_im;
(* mark_debug = "false" *) wire fft_ready;
(* mark_debug = "false" *) wire fft_done;
(* mark_debug = "false" *) wire fft_busy;
(* mark_debug = "false" *) wire fft_valid;
wire fft_in_stb;
reg fft_loading;
wire signed [15:0] fft_in_re;
wire signed [15:0] fft_in_im;
wire [22:0] fft_out_re;
wire [22:0] fft_out_im;
wire fft_ready;
wire fft_done;
wire fft_busy;
wire fft_valid;
wire [31:0] fft_out = {fft_out_re[22:7], fft_out_im[22:7]};
@ -145,15 +145,15 @@ wire signed [15:0] raw_q;
reg raw_stb;
wire idle_line1, idle_line2 ;
reg fft_din_data_tlast ;
(* mark_debug = "false" *) wire fft_din_data_tlast_delayed ;
(* mark_debug = "false" *) wire event_frame_started;
(* mark_debug = "false" *) wire event_tlast_unexpected;
(* mark_debug = "false" *) wire event_tlast_missing;
(* mark_debug = "false" *) wire event_status_channel_halt;
(* mark_debug = "false" *) wire event_data_in_channel_halt;
(* mark_debug = "false" *) wire event_data_out_channel_halt;
(* mark_debug = "false" *) wire s_axis_config_tready;
(* mark_debug = "false" *) wire m_axis_data_tlast;
wire fft_din_data_tlast_delayed ;
wire event_frame_started;
wire event_tlast_unexpected;
wire event_tlast_missing;
wire event_status_channel_halt;
wire event_data_in_channel_halt;
wire event_data_out_channel_halt;
wire s_axis_config_tready;
wire m_axis_data_tlast;
ram_2port #(.DWIDTH(32), .AWIDTH(IN_BUF_LEN_SHIFT)) in_buf (
.clka(clock),