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xjiao update: add soft decoding register switch

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mmehari 2019-12-10 13:48:38 +01:00
parent 1f8bb83587
commit 66aef6310f
2 changed files with 18 additions and 17 deletions
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7
verilog/openofdm_rx.v
View File

@ -60,8 +60,8 @@
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg1; // wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg1; //
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg2; wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg2;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg3; // wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg3; //
/*
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg4; // wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg4; //
/*
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg5; // wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg5; //
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg6; // wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg6; //
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg7; // wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg7; //
@ -121,6 +121,7 @@
.sample_in(sample_in), .sample_in(sample_in),
.sample_in_strobe(sample_in_strobe), .sample_in_strobe(sample_in_strobe),
.soft_decoding(slv_reg4[0]),
// OUTPUT: bytes and FCS status // OUTPUT: bytes and FCS status
.demod_is_ongoing(demod_is_ongoing), .demod_is_ongoing(demod_is_ongoing),
@ -233,8 +234,8 @@
.SLV_REG0(slv_reg0), .SLV_REG0(slv_reg0),
.SLV_REG1(slv_reg1), .SLV_REG1(slv_reg1),
.SLV_REG2(slv_reg2), .SLV_REG2(slv_reg2),
.SLV_REG3(slv_reg3), /*, .SLV_REG3(slv_reg3),
.SLV_REG4(slv_reg4), .SLV_REG4(slv_reg4), /*,
.SLV_REG5(slv_reg5), .SLV_REG5(slv_reg5),
.SLV_REG6(slv_reg6), .SLV_REG6(slv_reg6),
.SLV_REG7(slv_reg7), .SLV_REG7(slv_reg7),

28
verilog/openofdm_rx_s_axi.v
View File

@ -18,8 +18,8 @@
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG0, output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG0,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG1, output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG1,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG2, output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG2,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG3,/* output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG3,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG4, output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG4,/*
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG5, output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG5,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG6, output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG6,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG7, output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG7,
@ -138,8 +138,8 @@
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0; reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1; reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2; reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;/* reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4; reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4;/*
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5; reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6; reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7; reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7;
@ -186,8 +186,8 @@
assign SLV_REG0 = slv_reg0; assign SLV_REG0 = slv_reg0;
assign SLV_REG1 = slv_reg1; assign SLV_REG1 = slv_reg1;
assign SLV_REG2 = slv_reg2; assign SLV_REG2 = slv_reg2;
assign SLV_REG3 = slv_reg3;/* assign SLV_REG3 = slv_reg3;
assign SLV_REG4 = slv_reg4; assign SLV_REG4 = slv_reg4;/*
assign SLV_REG5 = slv_reg5; assign SLV_REG5 = slv_reg5;
assign SLV_REG6 = slv_reg6; assign SLV_REG6 = slv_reg6;
assign SLV_REG7 = slv_reg7; assign SLV_REG7 = slv_reg7;
@ -295,8 +295,8 @@
slv_reg0 <= 32'h0; slv_reg0 <= 32'h0;
slv_reg1 <= 32'h0; slv_reg1 <= 32'h0;
slv_reg2 <= 32'h0; slv_reg2 <= 32'h0;
slv_reg3 <= 32'h0;/* slv_reg3 <= 32'h0;
slv_reg4 <= 32'h0; slv_reg4 <= 32'h0;/*
slv_reg5 <= 32'h0; slv_reg5 <= 32'h0;
slv_reg6 <= 32'h0; slv_reg6 <= 32'h0;
slv_reg7 <= 32'h0; slv_reg7 <= 32'h0;
@ -344,14 +344,14 @@
// Respective byte enables are asserted as per write strobes // Respective byte enables are asserted as per write strobes
// Slave register 3 // Slave register 3
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end /* end
5'h04: 5'h04:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes // Respective byte enables are asserted as per write strobes
// Slave register 4 // Slave register 4
slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end end /*
5'h05: 5'h05:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin if ( S_AXI_WSTRB[byte_index] == 1 ) begin
@ -545,8 +545,8 @@
slv_reg0 <= slv_reg0; slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1; slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2; slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;/* slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4; slv_reg4 <= slv_reg4;/*
slv_reg5 <= slv_reg5; slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6; slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7; slv_reg7 <= slv_reg7;
@ -685,8 +685,8 @@
5'h00 : reg_data_out <= slv_reg0; 5'h00 : reg_data_out <= slv_reg0;
5'h01 : reg_data_out <= slv_reg1; 5'h01 : reg_data_out <= slv_reg1;
5'h02 : reg_data_out <= slv_reg2; 5'h02 : reg_data_out <= slv_reg2;
5'h03 : reg_data_out <= slv_reg3;/* 5'h03 : reg_data_out <= slv_reg3;
5'h04 : reg_data_out <= slv_reg4; 5'h04 : reg_data_out <= slv_reg4;/*
5'h05 : reg_data_out <= slv_reg5; 5'h05 : reg_data_out <= slv_reg5;
5'h06 : reg_data_out <= slv_reg6; 5'h06 : reg_data_out <= slv_reg6;
5'h07 : reg_data_out <= slv_reg7; 5'h07 : reg_data_out <= slv_reg7;