From 3f645e30f464db2642f8c02ef01d1fc33e2a0a03 Mon Sep 17 00:00:00 2001 From: Xianjun Jiao Date: Mon, 9 Jan 2023 16:00:47 +0100 Subject: [PATCH] Add antsdr/e200 and sdrpi --- create_vivado_proj.sh | 2 +- parse_board_name.tcl | 4 ---- verilog/openofdm_rx.v | 1 - 3 files changed, 1 insertion(+), 6 deletions(-) diff --git a/create_vivado_proj.sh b/create_vivado_proj.sh index ea0e493..cbdc77d 100755 --- a/create_vivado_proj.sh +++ b/create_vivado_proj.sh @@ -9,7 +9,7 @@ print_usage () { echo "Need at least 2 arguments: \$XILINX_DIR \$TCL_FILENAME" echo "More arguments (max 7) will be passed as arguments to the .tcl script to create ip_name_pre_def.v" echo "Among these max 7 arguments:" - echo "- the 1st: BOARD_NAME (sdrpi antsdr zc706_fmcs2 zed_fmcs2 zc702_fmcs2 adrv9361z7035 adrv9364z7020 zcu102_fmcs2)" + echo "- the 1st: BOARD_NAME (antsdr antsdr_e200 sdrpi zc706_fmcs2 zed_fmcs2 zc702_fmcs2 adrv9361z7035 adrv9364z7020 zcu102_fmcs2)" echo "- the 2nd: NUM_CLK_PER_US (for example: input 100 for 100MHz)" echo "- the 3rd-7th: User pre defines (assume it is ABC) for conditional compiling. Will be \`define IP_NAME_ABC in ip_name_pre_def.v" echo " - the 3rd exception: in the case of openofdm_rx, it indicates SAMPLE_FILE for simulation. Can be changed later in openofdm_rx_pre_def.v" diff --git a/parse_board_name.tcl b/parse_board_name.tcl index 63c8413..dbe6b23 100644 --- a/parse_board_name.tcl +++ b/parse_board_name.tcl @@ -40,10 +40,6 @@ if {$BOARD_NAME=="zed_fmcs2"} { set ultra_scale_flag 0 set part_string xc7z020clg400-1 set fpga_size_flag 0 -} elseif {$BOARD_NAME=="neptunesdr"} { - set ultra_scale_flag 0 - set part_string xc7z020clg400-1 - set fpga_size_flag 0 } else { set ultra_scale_flag [] set part_string [] diff --git a/verilog/openofdm_rx.v b/verilog/openofdm_rx.v index b736f45..b5fc8ff 100644 --- a/verilog/openofdm_rx.v +++ b/verilog/openofdm_rx.v @@ -326,4 +326,3 @@ ); endmodule -