From 297162af1350403bdcca515547bdbd2570af1184 Mon Sep 17 00:00:00 2001 From: Jinghao Shi Date: Fri, 7 Apr 2017 16:51:06 -0400 Subject: [PATCH] working --- docs/source/sync_long.rst | 5 +++-- verilog/dot11_tb.v | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/docs/source/sync_long.rst b/docs/source/sync_long.rst index dd08526..53eb213 100644 --- a/docs/source/sync_long.rst +++ b/docs/source/sync_long.rst @@ -96,6 +96,7 @@ a portion instead of all the LTS samples. matched filter with different size. It can be seen that using the first 16 samples of LTS is good enough to exhibit two narrow spikes. Therefore, |project| use matched filter of size 16 for symbol alignment. And the first sample of the -long preamble starts at :math:`N_{16}-57`, where :math:`N_{16}` is the index of the -first spike when the filter size is 16 (:math:`N_{32}-49` when filter size is +long preamble starts at :math:`N_{16}-57`, where :math:`N_{16}` is the index of +the first spike when the filter size is 16 (for completeness, it is +:math:`N_{32}-49` when filter size is 32). diff --git a/verilog/dot11_tb.v b/verilog/dot11_tb.v index ee46205..d6dba24 100644 --- a/verilog/dot11_tb.v +++ b/verilog/dot11_tb.v @@ -80,7 +80,7 @@ integer signal_fd; integer byte_out_fd; `ifndef SAMPLE_FILE -`define SAMPLE_FILE "../testing_inputs/conducted/dot11a_6mbps_qos_data_e4_90_7e_15_2a_16_e8_de_27_90_6e_42.txt" +`define SAMPLE_FILE "../testing_inputs/conducted/dot11a_24mbps_qos_data_e4_90_7e_15_2a_16_e8_de_27_90_6e_42.txt" `endif `ifndef NUM_SAMPLE