mirror of
https://github.com/jhshi/openofdm.git
synced 2024-12-23 23:43:06 +00:00
necessary bug fixes and improvements for openwifi
This commit is contained in:
parent
10ff8da3d7
commit
2643844f2f
@ -1,8 +1,6 @@
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#*****************************************************************************************
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#*****************************************************************************************
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# Vivado (TM) v2017.4.1 (64-bit)
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# Vivado (TM) v2017.4.1 (64-bit)
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#
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#
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# ip_gen_test1.tcl: Tcl script for re-creating project 'edit_power_trigger_axi4_v1_0'
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#
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# Generated by Vivado on Mon Jan 21 11:32:41 +0100 2019
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# Generated by Vivado on Mon Jan 21 11:32:41 +0100 2019
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# IP Build 2095745 on Tue Jan 30 17:13:15 MST 2018
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# IP Build 2095745 on Tue Jan 30 17:13:15 MST 2018
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#
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#
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@ -14,24 +12,6 @@
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# original project, however they will not be launched automatically. To regenerate the
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# original project, however they will not be launched automatically. To regenerate the
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# run results please launch the synthesis/implementation runs as needed.
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# run results please launch the synthesis/implementation runs as needed.
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#
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#
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#*****************************************************************************************
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# NOTE: In order to use this script for source control purposes, please make sure that the
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# following files are added to the source control system:-
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#
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# 1. This project restoration tcl script (ip_gen_test1.tcl) that was generated.
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#
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# 2. The following source(s) files that were local or imported into the original project.
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# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
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#
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# "C:/Users/lwei/Downloads/ip_repo-20190121T095109Z-001/ip_repo/power_trigger_axi4_1.0/src/delayT.v"
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# "C:/Users/lwei/Downloads/ip_repo-20190121T095109Z-001/ip_repo/power_trigger_axi4_1.0/src/power_trigger.v"
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# "C:/Users/lwei/Downloads/ip_repo-20190121T095109Z-001/ip_repo/power_trigger_axi4_1.0/hdl/power_trigger_axi4_v1_0_S00_AXI.v"
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# "C:/Users/lwei/Downloads/ip_repo-20190121T095109Z-001/ip_repo/power_trigger_axi4_1.0/hdl/power_trigger_axi4_v1_0.v"
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# "C:/Users/lwei/Downloads/ip_repo-20190121T095109Z-001/ip_repo/power_trigger_axi4_1.0/component.xml"
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#
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# 3. The following remote source files that were added to the original project:-
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#
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# <none>
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#
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#
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#*****************************************************************************************
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#*****************************************************************************************
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@ -44,7 +24,7 @@ if { [info exists ::origin_dir_loc] } {
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}
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}
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# Set the project name
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# Set the project name
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set project_name "edit_dot11_axi4_ip"
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set project_name "openofdm_rx"
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# Use project name variable, if specified in the tcl shell
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# Use project name variable, if specified in the tcl shell
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if { [info exists ::user_project_name] } {
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if { [info exists ::user_project_name] } {
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@ -52,7 +32,7 @@ if { [info exists ::user_project_name] } {
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}
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}
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variable script_file
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variable script_file
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set script_file "axi4_ip_gen.tcl"
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set script_file "openofdm_rx.tcl"
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# Help information for this script
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# Help information for this script
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proc help {} {
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proc help {} {
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@ -164,18 +144,17 @@ set files [list \
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"[file normalize "$origin_dir/verilog/moving_avg.v"]"\
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"[file normalize "$origin_dir/verilog/moving_avg.v"]"\
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"[file normalize "$origin_dir/verilog/ofdm_decoder.v"]"\
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"[file normalize "$origin_dir/verilog/ofdm_decoder.v"]"\
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"[file normalize "$origin_dir/verilog/phase.v"]"\
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"[file normalize "$origin_dir/verilog/phase.v"]"\
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"[file normalize "$origin_dir/verilog/power_trigger.v"]"\
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"[file normalize "$origin_dir/verilog/openofdm_rx_s_axi.v"]"\
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"[file normalize "$origin_dir/verilog/dot11zynq_S00_AXI.v"]"\
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"[file normalize "$origin_dir/verilog/usrp2/ram_2port.v"]"\
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"[file normalize "$origin_dir/verilog/usrp2/ram_2port.v"]"\
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"[file normalize "$origin_dir/verilog/rotate.v"]"\
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"[file normalize "$origin_dir/verilog/rotate.v"]"\
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"[file normalize "$origin_dir/verilog/stage_mult.v"]"\
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"[file normalize "$origin_dir/verilog/stage_mult.v"]"\
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"[file normalize "$origin_dir/verilog/sync_long.v"]"\
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"[file normalize "$origin_dir/verilog/sync_long.v"]"\
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"[file normalize "$origin_dir/verilog/sync_short.v"]"\
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"[file normalize "$origin_dir/verilog/sync_short.v"]"\
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"[file normalize "$origin_dir/verilog/dot11zynq.v"]"\
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"[file normalize "$origin_dir/verilog/openofdm_rx.v"]"\
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"[file normalize "$origin_dir/verilog/Xilinx/vivado2017.4.1/deinter_lut/deinter_lut.coe"]"\
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"[file normalize "$origin_dir/verilog/Xilinx/vivado2017.4.1/deinter_lut/deinter_lut.coe"]"\
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"[file normalize "$origin_dir/verilog/Xilinx/vivado2017.4.1/atan_lut/atan_lut.coe"]"\
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"[file normalize "$origin_dir/verilog/Xilinx/vivado2017.4.1/atan_lut/atan_lut.coe"]"\
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"[file normalize "$origin_dir/verilog/Xilinx/vivado2017.4.1/rot_lut/rot_lut.coe"]"\
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"[file normalize "$origin_dir/verilog/Xilinx/vivado2017.4.1/rot_lut/rot_lut.coe"]"\
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"[file normalize "$origin_dir/verilog/intf_64bit.v"]"\
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"[file normalize "$origin_dir/../rx_intf/src/byte_to_word_fcs_sn_insert.v"]"\
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]
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]
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# If you want to make a copy of the file to new src folder, use following command
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# If you want to make a copy of the file to new src folder, use following command
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# set imported_files [import_files -fileset sources_1 $files]
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# set imported_files [import_files -fileset sources_1 $files]
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@ -189,12 +168,12 @@ set file [file normalize $file]
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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set_property -name "file_type" -value "NGC" -objects $file_obj
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set_property -name "file_type" -value "NGC" -objects $file_obj
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set file "dot11zynq_S00_AXI.v"
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set file "openofdm_rx_s_axi.v"
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
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set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
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set_property -name "used_in_implementation" -value "0" -objects $file_obj
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set_property -name "used_in_implementation" -value "0" -objects $file_obj
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set file "dot11zynq.v"
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set file "openofdm_rx.v"
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
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set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
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set_property -name "used_in_implementation" -value "0" -objects $file_obj
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set_property -name "used_in_implementation" -value "0" -objects $file_obj
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@ -204,7 +183,7 @@ set_property -name "used_in_implementation" -value "0" -objects $file_obj
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# Set 'sources_1' fileset properties
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# Set 'sources_1' fileset properties
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set obj [get_filesets sources_1]
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set obj [get_filesets sources_1]
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set_property -name "top" -value "dot11zynq" -objects $obj
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set_property -name "top" -value "openofdm_rx" -objects $obj
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# Create 'constrs_1' fileset (if not found)
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# Create 'constrs_1' fileset (if not found)
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if {[string equal [get_filesets -quiet constrs_1] ""]} {
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if {[string equal [get_filesets -quiet constrs_1] ""]} {
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@ -230,7 +209,7 @@ if {[string equal [get_filesets -quiet sim_1] ""]} {
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# Set 'sim_1' fileset object
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# Set 'sim_1' fileset object
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set obj [get_filesets sim_1]
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set obj [get_filesets sim_1]
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set files [list \
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set files [list \
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"[file normalize "$origin_dir/verilog/dot11_tb.v"]"\
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"[file normalize "$origin_dir/verilog/dot11_tb.v"]"
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]
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]
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add_files -norecurse -fileset $obj $files
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add_files -norecurse -fileset $obj $files
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# Empty (no sources present)
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# Empty (no sources present)
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@ -102,7 +102,7 @@ def do_rate(rate=6, mcs=0, ht=False):
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erase = '5/6'
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erase = '5/6'
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else:
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else:
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n_bpsc = decode.RATE_PARAMETERS[rate][0]
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n_bpsc = decode.RATE_PARAMETERS[rate][0]
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if rate in [9, 18, 36]:
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if rate in [9, 18, 36, 54]:
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erase = '3/4'
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erase = '3/4'
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elif rate == 48:
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elif rate == 48:
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erase = '2/3'
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erase = '2/3'
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -131,7 +131,7 @@
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2017.4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2017.4.1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
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</spirit:configurableElementValues>
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</spirit:configurableElementValues>
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<spirit:vendorExtensions>
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<spirit:vendorExtensions>
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@ -161,6 +161,8 @@
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.TDEST_WIDTH" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.TDEST_WIDTH" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.TID_WIDTH" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.TID_WIDTH" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.APortWidth" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.BPortWidth" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.LatencyConfig" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.LatencyConfig" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MinimumLatency" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MinimumLatency" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OptimizeGoal" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OptimizeGoal" xilinx:valueSource="user"/>
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File diff suppressed because it is too large
Load Diff
@ -83,8 +83,8 @@
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">11</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">12</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">11</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">12</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
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@ -92,7 +92,7 @@
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLK">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLK">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_18K_BRAM">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_18K_BRAM">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_36K_BRAM">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_36K_BRAM">2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
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@ -106,7 +106,7 @@
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
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||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:configurableElementValue>
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||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP : 3.6199499999999998 mW</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP : 5.8919990000000002 mW</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
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||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">0</spirit:configurableElementValue>
|
||||||
@ -131,8 +131,8 @@
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|||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">3</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">3</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">2048</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">4096</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">2048</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">4096</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">22</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">22</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_B">22</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_B">22</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:configurableElementValue>
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||||||
@ -149,8 +149,8 @@
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|||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">2048</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">4096</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">2048</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">4096</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">22</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">22</spirit:configurableElementValue>
|
||||||
@ -218,7 +218,7 @@
|
|||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">2048</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">4096</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">22</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">22</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">22</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">22</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
|
||||||
|
@ -106,7 +106,7 @@
|
|||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP : 5.244 mW</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP : 5.2439999999999998 mW</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">0</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">0</spirit:configurableElementValue>
|
||||||
|
@ -105,7 +105,7 @@
|
|||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DATA_TDATA_WIDTH">16</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DATA_TDATA_WIDTH">16</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DATA_TUSER_WIDTH">8</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DATA_TUSER_WIDTH">8</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DSTAT_TDATA_WIDTH">16</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DSTAT_TDATA_WIDTH">16</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRACEBACK_LENGTH">24</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRACEBACK_LENGTH">84</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRELLIS_MODE">0</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRELLIS_MODE">0</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">zynq</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">zynq</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">true</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">true</spirit:configurableElementValue>
|
||||||
@ -118,8 +118,8 @@
|
|||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coding">Soft_Coding</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coding">Soft_Coding</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">viterbi_v7_0</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">viterbi_v7_0</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Constraint_Length">7</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Constraint_Length">7</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Convolution0_Code0">133</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Convolution0_Code0">1011011</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Convolution0_Code1">171</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Convolution0_Code1">1111001</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Convolution0_Code2">0</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Convolution0_Code2">0</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Convolution0_Code3">0</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Convolution0_Code3">0</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Convolution0_Code4">0</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Convolution0_Code4">0</spirit:configurableElementValue>
|
||||||
@ -132,7 +132,7 @@
|
|||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Convolution1_Code4">0</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Convolution1_Code4">0</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Convolution1_Code5">0</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Convolution1_Code5">0</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Convolution1_Code6">0</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Convolution1_Code6">0</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Convolution_Code_0_Radix">Octal</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Convolution_Code_0_Radix">Binary</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Convolution_Code_1_Radix">Binary</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Convolution_Code_1_Radix">Binary</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Format">Signed_Magnitude</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Format">Signed_Magnitude</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Norm">false</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Norm">false</spirit:configurableElementValue>
|
||||||
@ -142,7 +142,7 @@
|
|||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reduced_Latency">true</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reduced_Latency">true</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Soft_Width">3</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Soft_Width">3</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TREADY">false</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TREADY">false</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Traceback_Length">24</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Traceback_Length">84</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Viterbi_Type">Standard</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Viterbi_Type">Standard</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD">xilinx.com:zc706:part0:1.4</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD">xilinx.com:zc706:part0:1.4</spirit:configurableElementValue>
|
||||||
@ -199,6 +199,7 @@
|
|||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DSTAT.TUSER_WIDTH" xilinx:valueSource="constant"/>
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DSTAT.TUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLKEN" xilinx:valueSource="user"/>
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLKEN" xilinx:valueSource="user"/>
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.BER_Symbol_Count" xilinx:valueSource="user"/>
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.BER_Symbol_Count" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Best_State" xilinx:valueSource="user"/>
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Convolution0_Code0" xilinx:valueSource="user"/>
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Convolution0_Code0" xilinx:valueSource="user"/>
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Convolution0_Code1" xilinx:valueSource="user"/>
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Convolution0_Code1" xilinx:valueSource="user"/>
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Convolution_Code_0_Radix" xilinx:valueSource="user"/>
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Convolution_Code_0_Radix" xilinx:valueSource="user"/>
|
||||||
|
@ -6,7 +6,7 @@
|
|||||||
<spirit:version>1.0</spirit:version>
|
<spirit:version>1.0</spirit:version>
|
||||||
<spirit:componentInstances>
|
<spirit:componentInstances>
|
||||||
<spirit:componentInstance>
|
<spirit:componentInstance>
|
||||||
<spirit:instanceName>xfft_v7_1</spirit:instanceName>
|
<spirit:instanceName>xfft_v9</spirit:instanceName>
|
||||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xfft" spirit:version="9.0"/>
|
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xfft" spirit:version="9.0"/>
|
||||||
<spirit:configurableElementValues>
|
<spirit:configurableElementValues>
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||||
@ -70,7 +70,7 @@
|
|||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TUSER_WIDTH">0</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TUSER_WIDTH">0</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ARCH">3</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ARCH">3</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BFLY_TYPE">0</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BFLY_TYPE">0</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BRAM_STAGES">1</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BRAM_STAGES">0</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CHANNELS">1</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CHANNELS">1</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CMPY_TYPE">1</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CMPY_TYPE">1</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_MEM_TYPE">1</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_MEM_TYPE">1</spirit:configurableElementValue>
|
||||||
@ -115,14 +115,14 @@
|
|||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.memory_options_hybrid">false</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.memory_options_hybrid">false</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.memory_options_phase_factors">block_ram</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.memory_options_phase_factors">block_ram</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.memory_options_reorder">block_ram</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.memory_options_reorder">block_ram</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.number_of_stages_using_block_ram_for_data_and_phase_factors">1</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.number_of_stages_using_block_ram_for_data_and_phase_factors">0</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.output_ordering">natural_order</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.output_ordering">natural_order</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ovflo">false</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ovflo">false</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_factor_width">16</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_factor_width">16</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rounding_modes">truncation</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rounding_modes">truncation</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.run_time_configurable_transform_length">false</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.run_time_configurable_transform_length">false</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.scaling_options">unscaled</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.scaling_options">unscaled</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.target_clock_frequency">100</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.target_clock_frequency">200</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.target_data_throughput">50</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.target_data_throughput">50</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.throttle_scheme">nonrealtime</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.throttle_scheme">nonrealtime</spirit:configurableElementValue>
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.transform_length">64</spirit:configurableElementValue>
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.transform_length">64</spirit:configurableElementValue>
|
||||||
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -24,7 +24,7 @@ wire [5:0] half_data_carrier = ht? 26: 24;
|
|||||||
reg [5:0] addra;
|
reg [5:0] addra;
|
||||||
reg [5:0] addrb;
|
reg [5:0] addrb;
|
||||||
|
|
||||||
reg [10:0] lut_key;
|
reg [11:0] lut_key;
|
||||||
wire [21:0] lut_out;
|
wire [21:0] lut_out;
|
||||||
wire [21:0] lut_out_delayed;
|
wire [21:0] lut_out_delayed;
|
||||||
|
|
||||||
@ -85,7 +85,7 @@ localparam S_INPUT = 0;
|
|||||||
localparam S_GET_BASE = 1;
|
localparam S_GET_BASE = 1;
|
||||||
localparam S_OUTPUT = 2;
|
localparam S_OUTPUT = 2;
|
||||||
|
|
||||||
reg [1:0] state;
|
(* mark_debug = "true" *) reg [1:0] state;
|
||||||
|
|
||||||
always @(posedge clock) begin
|
always @(posedge clock) begin
|
||||||
if (reset) begin
|
if (reset) begin
|
||||||
@ -108,7 +108,7 @@ always @(posedge clock) begin
|
|||||||
S_INPUT: begin
|
S_INPUT: begin
|
||||||
if (input_strobe) begin
|
if (input_strobe) begin
|
||||||
if (addra == half_data_carrier-1) begin
|
if (addra == half_data_carrier-1) begin
|
||||||
lut_key <= {6'b0, ht, rate[3:0]};
|
lut_key <= {7'b0, ht, rate[3:0]};
|
||||||
ram_delay <= 0;
|
ram_delay <= 0;
|
||||||
lut_valid <= 0;
|
lut_valid <= 0;
|
||||||
state <= S_GET_BASE;
|
state <= S_GET_BASE;
|
||||||
|
207
verilog/dot11.v
207
verilog/dot11.v
@ -11,40 +11,43 @@ module dot11 (
|
|||||||
//input [31:0] set_data,
|
//input [31:0] set_data,
|
||||||
|
|
||||||
// add ports for register based inputs
|
// add ports for register based inputs
|
||||||
input [15:0] power_thres,
|
input [10:0] power_thres,
|
||||||
input [15:0] window_size,
|
|
||||||
input [31:0] num_sample_to_skip,
|
|
||||||
input num_sample_changed,
|
|
||||||
input [31:0] min_plateau,
|
input [31:0] min_plateau,
|
||||||
|
|
||||||
|
// INPUT: RSSI
|
||||||
|
input [10:0] rssi_half_db,
|
||||||
// INPUT: I/Q sample
|
// INPUT: I/Q sample
|
||||||
input [31:0] sample_in,
|
(* mark_debug = "true" *) input [31:0] sample_in,
|
||||||
input sample_in_strobe,
|
(* mark_debug = "true" *) input sample_in_strobe,
|
||||||
|
|
||||||
// OUTPUT: bytes and FCS status
|
// OUTPUT: bytes and FCS status
|
||||||
output reg pkt_begin,
|
(* mark_debug = "true" *) output reg demod_is_ongoing,
|
||||||
output reg pkt_ht,
|
(* mark_debug = "true" *) output reg pkt_begin,
|
||||||
output reg [7:0] pkt_rate,
|
(* mark_debug = "true" *) output reg pkt_ht,
|
||||||
output reg [15:0] pkt_len,
|
(* mark_debug = "true" *) output reg pkt_header_valid,
|
||||||
output byte_out_strobe,
|
(* mark_debug = "true" *) output reg pkt_header_valid_strobe,
|
||||||
output [7:0] byte_out,
|
(* mark_debug = "true" *) output reg ht_unsupport,
|
||||||
output reg fcs_out_strobe,
|
(* mark_debug = "true" *) output reg [7:0] pkt_rate,
|
||||||
output reg fcs_ok,
|
(* mark_debug = "true" *) output reg [15:0] pkt_len,
|
||||||
output wire [63:0] data_out,
|
(* mark_debug = "true" *) output reg [15:0] pkt_len_total,
|
||||||
output wire data_out_valid,
|
(* mark_debug = "true" *) output byte_out_strobe,
|
||||||
|
(* mark_debug = "true" *) output [7:0] byte_out,
|
||||||
|
(* mark_debug = "true" *) output reg [15:0] byte_count_total,
|
||||||
|
(* mark_debug = "true" *) output reg [15:0] byte_count,
|
||||||
|
(* mark_debug = "true" *) output reg fcs_out_strobe,
|
||||||
|
(* mark_debug = "true" *) output reg fcs_ok,
|
||||||
|
|
||||||
/////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////
|
||||||
// DEBUG PORTS
|
// DEBUG PORTS
|
||||||
/////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////
|
||||||
|
|
||||||
// decode status
|
// decode status
|
||||||
output reg [3:0] state,
|
(* mark_debug = "true" *) output reg [3:0] state,
|
||||||
output reg [3:0] status_code,
|
(* mark_debug = "true" *) output reg [3:0] status_code,
|
||||||
output state_changed,
|
output state_changed,
|
||||||
|
|
||||||
// power trigger
|
// power trigger
|
||||||
output power_trigger,
|
output power_trigger,
|
||||||
output [1:0] pw_state_spy,
|
|
||||||
|
|
||||||
// sync short
|
// sync short
|
||||||
output short_preamble_detected,
|
output short_preamble_detected,
|
||||||
@ -71,8 +74,6 @@ module dot11 (
|
|||||||
output legacy_sig_parity,
|
output legacy_sig_parity,
|
||||||
output legacy_sig_parity_ok,
|
output legacy_sig_parity_ok,
|
||||||
output [5:0] legacy_sig_tail,
|
output [5:0] legacy_sig_tail,
|
||||||
output [23:0] sig_bits_spy,
|
|
||||||
output [31:0] byte_count_spy,
|
|
||||||
|
|
||||||
// ht signal info
|
// ht signal info
|
||||||
output reg ht_sig_stb,
|
output reg ht_sig_stb,
|
||||||
@ -92,8 +93,8 @@ module dot11 (
|
|||||||
output [5:0] demod_out,
|
output [5:0] demod_out,
|
||||||
output demod_out_strobe,
|
output demod_out_strobe,
|
||||||
|
|
||||||
output [1:0] deinterleave_out,
|
output [3:0] deinterleave_erase_out,
|
||||||
output deinterleave_out_strobe,
|
output deinterleave_erase_out_strobe,
|
||||||
|
|
||||||
output conv_decoder_out,
|
output conv_decoder_out,
|
||||||
output conv_decoder_out_stb,
|
output conv_decoder_out_stb,
|
||||||
@ -172,10 +173,10 @@ phase phase_inst (
|
|||||||
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
(* mark_debug = "true" *) reg sync_short_reset;
|
reg sync_short_reset;
|
||||||
(* mark_debug = "true" *) reg sync_long_reset;
|
reg sync_long_reset;
|
||||||
(* mark_debug = "true" *) wire sync_short_enable = state == S_SYNC_SHORT;
|
wire sync_short_enable = state == S_SYNC_SHORT;
|
||||||
(* mark_debug = "true" *) reg sync_long_enable;
|
reg sync_long_enable;
|
||||||
|
|
||||||
reg equalizer_reset;
|
reg equalizer_reset;
|
||||||
reg equalizer_enable;
|
reg equalizer_enable;
|
||||||
@ -203,14 +204,13 @@ reg do_descramble;
|
|||||||
reg [31:0] num_bits_to_decode;
|
reg [31:0] num_bits_to_decode;
|
||||||
reg short_gi;
|
reg short_gi;
|
||||||
|
|
||||||
reg [3:0] old_state;
|
(* mark_debug = "true" *) reg [3:0] old_state;
|
||||||
|
|
||||||
|
assign power_trigger = (rssi_half_db>=power_thres? 1: 0);
|
||||||
assign state_changed = state != old_state;
|
assign state_changed = state != old_state;
|
||||||
|
|
||||||
// SIGNAL information
|
// SIGNAL information
|
||||||
reg [23:0] signal_bits;
|
(* mark_debug = "true" *) reg [23:0] signal_bits;
|
||||||
reg [31:0] byte_count;
|
|
||||||
assign sig_bits_spy = signal_bits;
|
|
||||||
assign byte_count_spy = byte_count ;
|
|
||||||
|
|
||||||
assign legacy_rate = signal_bits[3:0];
|
assign legacy_rate = signal_bits[3:0];
|
||||||
assign legacy_sig_rsvd = signal_bits[4];
|
assign legacy_sig_rsvd = signal_bits[4];
|
||||||
@ -221,8 +221,8 @@ assign legacy_sig_parity_ok = ~^signal_bits[17:0];
|
|||||||
|
|
||||||
|
|
||||||
// HT-SIG information
|
// HT-SIG information
|
||||||
reg [23:0] ht_sig1;
|
(* mark_debug = "true" *) reg [23:0] ht_sig1;
|
||||||
reg [23:0] ht_sig2;
|
(* mark_debug = "true" *) reg [23:0] ht_sig2;
|
||||||
|
|
||||||
assign ht_mcs = ht_sig1[6:0];
|
assign ht_mcs = ht_sig1[6:0];
|
||||||
assign ht_cbw = ht_sig1[7];
|
assign ht_cbw = ht_sig1[7];
|
||||||
@ -266,8 +266,7 @@ assign byte_reversed[7] = byte_out[0];
|
|||||||
|
|
||||||
reg [15:0] sync_long_out_count;
|
reg [15:0] sync_long_out_count;
|
||||||
|
|
||||||
integer i;
|
/*
|
||||||
|
|
||||||
power_trigger power_trigger_inst (
|
power_trigger power_trigger_inst (
|
||||||
.clock(clock),
|
.clock(clock),
|
||||||
.enable(enable),
|
.enable(enable),
|
||||||
@ -284,6 +283,7 @@ power_trigger power_trigger_inst (
|
|||||||
.pw_state_spy(pw_state_spy),
|
.pw_state_spy(pw_state_spy),
|
||||||
.trigger(power_trigger)
|
.trigger(power_trigger)
|
||||||
);
|
);
|
||||||
|
*/
|
||||||
|
|
||||||
sync_short sync_short_inst (
|
sync_short sync_short_inst (
|
||||||
.clock(clock),
|
.clock(clock),
|
||||||
@ -380,8 +380,8 @@ ofdm_decoder ofdm_decoder_inst (
|
|||||||
.demod_out(demod_out),
|
.demod_out(demod_out),
|
||||||
.demod_out_strobe(demod_out_strobe),
|
.demod_out_strobe(demod_out_strobe),
|
||||||
|
|
||||||
.deinterleave_out(deinterleave_out),
|
.deinterleave_erase_out(deinterleave_erase_out),
|
||||||
.deinterleave_out_strobe(deinterleave_out_strobe),
|
.deinterleave_erase_out_strobe(deinterleave_erase_out_strobe),
|
||||||
|
|
||||||
.conv_decoder_out(conv_decoder_out),
|
.conv_decoder_out(conv_decoder_out),
|
||||||
.conv_decoder_out_stb(conv_decoder_out_stb),
|
.conv_decoder_out_stb(conv_decoder_out_stb),
|
||||||
@ -408,21 +408,6 @@ crc32 fcs_inst (
|
|||||||
.crc_out(pkt_fcs)
|
.crc_out(pkt_fcs)
|
||||||
);
|
);
|
||||||
|
|
||||||
intf_64bit intf64bit_inst (
|
|
||||||
.clock(clock),
|
|
||||||
.reset(reset | sync_short_reset),
|
|
||||||
.enable(enable),
|
|
||||||
.pkt_len(pkt_len),
|
|
||||||
.byte_index(byte_count),
|
|
||||||
|
|
||||||
.byte_in(byte_out),
|
|
||||||
.byte_strobe(byte_out_strobe),
|
|
||||||
|
|
||||||
.data_out(data_out),
|
|
||||||
.output_strobe(data_out_valid)
|
|
||||||
);
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
always @(posedge clock) begin
|
always @(posedge clock) begin
|
||||||
if (reset) begin
|
if (reset) begin
|
||||||
@ -436,10 +421,14 @@ always @(posedge clock) begin
|
|||||||
sync_long_enable <= 0;
|
sync_long_enable <= 0;
|
||||||
|
|
||||||
byte_count <= 0;
|
byte_count <= 0;
|
||||||
|
byte_count_total <= 0;
|
||||||
|
|
||||||
|
demod_is_ongoing <= 0;
|
||||||
pkt_begin <= 0;
|
pkt_begin <= 0;
|
||||||
pkt_ht <= 0;
|
pkt_ht <= 0;
|
||||||
|
pkt_header_valid <= 0;
|
||||||
|
pkt_header_valid_strobe <= 0;
|
||||||
|
ht_unsupport <= 0;
|
||||||
|
|
||||||
rot_eq_count <= 0;
|
rot_eq_count <= 0;
|
||||||
normal_eq_count <= 0;
|
normal_eq_count <= 0;
|
||||||
@ -456,6 +445,7 @@ always @(posedge clock) begin
|
|||||||
ht_next <= 0;
|
ht_next <= 0;
|
||||||
|
|
||||||
pkt_len <= 0;
|
pkt_len <= 0;
|
||||||
|
pkt_len_total <= 0;
|
||||||
|
|
||||||
ofdm_reset <= 0;
|
ofdm_reset <= 0;
|
||||||
ofdm_enable <= 0;
|
ofdm_enable <= 0;
|
||||||
@ -486,9 +476,14 @@ always @(posedge clock) begin
|
|||||||
|
|
||||||
case(state)
|
case(state)
|
||||||
S_WAIT_POWER_TRIGGER: begin
|
S_WAIT_POWER_TRIGGER: begin
|
||||||
|
crc_reset <= 0;
|
||||||
|
short_gi <= 0;
|
||||||
|
demod_is_ongoing <= 0;
|
||||||
sync_long_enable <= 0;
|
sync_long_enable <= 0;
|
||||||
equalizer_enable <= 0;
|
equalizer_enable <= 0;
|
||||||
ofdm_enable <= 0;
|
ofdm_enable <= 0;
|
||||||
|
ofdm_reset <= 0;
|
||||||
|
pkt_len_total <= 16'hffff;
|
||||||
|
|
||||||
if (power_trigger) begin
|
if (power_trigger) begin
|
||||||
`ifdef DEBUG_PRINT
|
`ifdef DEBUG_PRINT
|
||||||
@ -538,6 +533,7 @@ always @(posedge clock) begin
|
|||||||
end
|
end
|
||||||
|
|
||||||
if (long_preamble_detected) begin
|
if (long_preamble_detected) begin
|
||||||
|
demod_is_ongoing <= 1;
|
||||||
pkt_rate <= {1'b0, 3'b0, 4'b1011};
|
pkt_rate <= {1'b0, 3'b0, 4'b1011};
|
||||||
do_descramble <= 0;
|
do_descramble <= 0;
|
||||||
num_bits_to_decode <= 48;
|
num_bits_to_decode <= 48;
|
||||||
@ -549,14 +545,13 @@ always @(posedge clock) begin
|
|||||||
equalizer_reset <= 1;
|
equalizer_reset <= 1;
|
||||||
|
|
||||||
byte_count <= 0;
|
byte_count <= 0;
|
||||||
|
byte_count_total <= 0;
|
||||||
state <= S_DECODE_SIGNAL;
|
state <= S_DECODE_SIGNAL;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
S_DECODE_SIGNAL: begin
|
S_DECODE_SIGNAL: begin
|
||||||
if (ofdm_reset) begin
|
|
||||||
ofdm_reset <= 0;
|
ofdm_reset <= 0;
|
||||||
end
|
|
||||||
|
|
||||||
if (equalizer_reset) begin
|
if (equalizer_reset) begin
|
||||||
equalizer_reset <= 0;
|
equalizer_reset <= 0;
|
||||||
@ -569,6 +564,7 @@ always @(posedge clock) begin
|
|||||||
if (byte_out_strobe) begin
|
if (byte_out_strobe) begin
|
||||||
signal_bits <= {byte_out, signal_bits[23:8]};
|
signal_bits <= {byte_out, signal_bits[23:8]};
|
||||||
byte_count <= byte_count + 1;
|
byte_count <= byte_count + 1;
|
||||||
|
byte_count_total <= byte_count_total + 1;
|
||||||
end
|
end
|
||||||
|
|
||||||
if (byte_count == 3) begin
|
if (byte_count == 3) begin
|
||||||
@ -579,25 +575,34 @@ always @(posedge clock) begin
|
|||||||
"parity = %b, ", legacy_sig_parity,
|
"parity = %b, ", legacy_sig_parity,
|
||||||
"tail = %6b", legacy_sig_tail);
|
"tail = %6b", legacy_sig_tail);
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
|
num_bits_to_decode <= (22+(legacy_len<<3))<<1;
|
||||||
|
pkt_rate <= {1'b0, 3'b0, legacy_rate};
|
||||||
|
pkt_len <= legacy_len;
|
||||||
|
pkt_len_total <= legacy_len+3;
|
||||||
|
|
||||||
ofdm_reset <= 1;
|
ofdm_reset <= 1;
|
||||||
state <= S_CHECK_SIGNAL;
|
state <= S_CHECK_SIGNAL;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
S_CHECK_SIGNAL: begin
|
S_CHECK_SIGNAL: begin
|
||||||
if (ofdm_reset) begin
|
|
||||||
ofdm_reset <= 0;
|
|
||||||
end
|
|
||||||
|
|
||||||
if (~legacy_sig_parity_ok) begin
|
if (~legacy_sig_parity_ok) begin
|
||||||
|
pkt_header_valid_strobe <= 1;
|
||||||
status_code <= E_PARITY_FAIL;
|
status_code <= E_PARITY_FAIL;
|
||||||
state <= S_SIGNAL_ERROR;
|
state <= S_SIGNAL_ERROR;
|
||||||
end else if (legacy_sig_rsvd) begin
|
end else if (legacy_sig_rsvd) begin
|
||||||
|
pkt_header_valid_strobe <= 1;
|
||||||
status_code <= E_WRONG_RSVD;
|
status_code <= E_WRONG_RSVD;
|
||||||
state <= S_SIGNAL_ERROR;
|
state <= S_SIGNAL_ERROR;
|
||||||
end else if (|legacy_sig_tail) begin
|
end else if (|legacy_sig_tail) begin
|
||||||
|
pkt_header_valid_strobe <= 1;
|
||||||
status_code <= E_WRONG_TAIL;
|
status_code <= E_WRONG_TAIL;
|
||||||
state <= S_SIGNAL_ERROR;
|
state <= S_SIGNAL_ERROR;
|
||||||
|
end else if (legacy_rate[3]==0) begin
|
||||||
|
pkt_header_valid_strobe <= 1;
|
||||||
|
status_code <= E_UNSUPPORTED_RATE;
|
||||||
|
state <= S_SIGNAL_ERROR;
|
||||||
end else begin
|
end else begin
|
||||||
legacy_sig_stb <= 1;
|
legacy_sig_stb <= 1;
|
||||||
status_code <= E_OK;
|
status_code <= E_OK;
|
||||||
@ -608,13 +613,11 @@ always @(posedge clock) begin
|
|||||||
normal_eq_count <= 0;
|
normal_eq_count <= 0;
|
||||||
state <= S_DETECT_HT;
|
state <= S_DETECT_HT;
|
||||||
end else begin
|
end else begin
|
||||||
pkt_rate <= {1'b0, 3'b0, legacy_rate};
|
//num_bits_to_decode <= (legacy_len+3)<<4;
|
||||||
num_bits_to_decode <= (legacy_len+3)<<4;
|
|
||||||
do_descramble <= 1;
|
do_descramble <= 1;
|
||||||
ofdm_reset <= 1;
|
ofdm_reset <= 1;
|
||||||
byte_count <= 0;
|
pkt_header_valid <= 1;
|
||||||
pkt_len <= legacy_len;
|
pkt_header_valid_strobe <= 1;
|
||||||
byte_count <= 0;
|
|
||||||
pkt_begin <= 1;
|
pkt_begin <= 1;
|
||||||
pkt_ht <= 0;
|
pkt_ht <= 0;
|
||||||
state <= S_DECODE_DATA;
|
state <= S_DECODE_DATA;
|
||||||
@ -623,11 +626,15 @@ always @(posedge clock) begin
|
|||||||
end
|
end
|
||||||
|
|
||||||
S_SIGNAL_ERROR: begin
|
S_SIGNAL_ERROR: begin
|
||||||
|
pkt_header_valid_strobe <= 0;
|
||||||
|
byte_count <= 0;
|
||||||
|
byte_count_total <= 0;
|
||||||
state <= S_WAIT_POWER_TRIGGER;
|
state <= S_WAIT_POWER_TRIGGER;
|
||||||
end
|
end
|
||||||
|
|
||||||
S_DETECT_HT: begin
|
S_DETECT_HT: begin
|
||||||
legacy_sig_stb <= 0;
|
legacy_sig_stb <= 0;
|
||||||
|
ofdm_reset <= 1;
|
||||||
|
|
||||||
if (equalizer_out_strobe) begin
|
if (equalizer_out_strobe) begin
|
||||||
abs_eq_i <= eq_out_i[15]? ~eq_out_i+1: eq_out_i;
|
abs_eq_i <= eq_out_i[15]? ~eq_out_i+1: eq_out_i;
|
||||||
@ -641,18 +648,14 @@ always @(posedge clock) begin
|
|||||||
|
|
||||||
if (rot_eq_count >= 4) begin
|
if (rot_eq_count >= 4) begin
|
||||||
// HT-SIG detected
|
// HT-SIG detected
|
||||||
byte_count <= 0;
|
|
||||||
pkt_rate <= {1'b0, 3'b0, 4'b1011};
|
|
||||||
num_bits_to_decode <= 96;
|
num_bits_to_decode <= 96;
|
||||||
do_descramble <= 0;
|
do_descramble <= 0;
|
||||||
ofdm_reset <= 1;
|
|
||||||
state <= S_HT_SIGNAL;
|
state <= S_HT_SIGNAL;
|
||||||
end else if (normal_eq_count > 4) begin
|
end else if (normal_eq_count > 4) begin
|
||||||
pkt_len <= legacy_len;
|
//num_bits_to_decode <= (legacy_len+3)<<4;
|
||||||
num_bits_to_decode <= (legacy_len+3)<<4;
|
|
||||||
do_descramble <= 1;
|
do_descramble <= 1;
|
||||||
ofdm_reset <= 1;
|
pkt_header_valid <= 1;
|
||||||
byte_count <= 0;
|
pkt_header_valid_strobe <= 1;
|
||||||
pkt_begin <= 1;
|
pkt_begin <= 1;
|
||||||
pkt_ht <= 0;
|
pkt_ht <= 0;
|
||||||
state <= S_DECODE_DATA;
|
state <= S_DECODE_DATA;
|
||||||
@ -660,9 +663,7 @@ always @(posedge clock) begin
|
|||||||
end
|
end
|
||||||
|
|
||||||
S_HT_SIGNAL: begin
|
S_HT_SIGNAL: begin
|
||||||
if (ofdm_reset) begin
|
|
||||||
ofdm_reset <= 0;
|
ofdm_reset <= 0;
|
||||||
end
|
|
||||||
|
|
||||||
ofdm_in_stb <= eq_out_stb_delayed;
|
ofdm_in_stb <= eq_out_stb_delayed;
|
||||||
// rotate clockwise by 90 degree
|
// rotate clockwise by 90 degree
|
||||||
@ -676,6 +677,7 @@ always @(posedge clock) begin
|
|||||||
ht_sig2 <= {byte_out, ht_sig2[23:8]};
|
ht_sig2 <= {byte_out, ht_sig2[23:8]};
|
||||||
end
|
end
|
||||||
byte_count <= byte_count + 1;
|
byte_count <= byte_count + 1;
|
||||||
|
byte_count_total <= byte_count_total + 1;
|
||||||
end
|
end
|
||||||
|
|
||||||
if (byte_count == 6) begin
|
if (byte_count == 6) begin
|
||||||
@ -693,6 +695,12 @@ always @(posedge clock) begin
|
|||||||
"crc = %08b, ", crc,
|
"crc = %08b, ", crc,
|
||||||
"tail = %06b", ht_sig_tail);
|
"tail = %06b", ht_sig_tail);
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
|
num_bits_to_decode <= (22+(ht_len<<3))<<1;
|
||||||
|
pkt_rate <= {1'b1, ht_mcs};
|
||||||
|
pkt_len <= ht_len;
|
||||||
|
pkt_len_total <= ht_len+3+6; //(6 bytes for 3 byte HT-SIG1 and 3 byte HT-SIG2)
|
||||||
|
|
||||||
crc_count <= 0;
|
crc_count <= 0;
|
||||||
crc_reset <= 1;
|
crc_reset <= 1;
|
||||||
crc_in_stb <= 0;
|
crc_in_stb <= 0;
|
||||||
@ -702,6 +710,7 @@ always @(posedge clock) begin
|
|||||||
end
|
end
|
||||||
|
|
||||||
S_CHECK_HT_SIG_CRC: begin
|
S_CHECK_HT_SIG_CRC: begin
|
||||||
|
ofdm_reset <= 1;
|
||||||
crc_reset <= 0;
|
crc_reset <= 0;
|
||||||
crc_count <= crc_count + 1;
|
crc_count <= crc_count + 1;
|
||||||
|
|
||||||
@ -714,47 +723,58 @@ always @(posedge clock) begin
|
|||||||
end else if (crc_count == 34) begin
|
end else if (crc_count == 34) begin
|
||||||
crc_in_stb <= 0;
|
crc_in_stb <= 0;
|
||||||
end else if (crc_count == 35) begin
|
end else if (crc_count == 35) begin
|
||||||
if (crc_out ^ crc) begin
|
|
||||||
status_code <= E_WRONG_CRC;
|
|
||||||
ht_sig_stb <= 1;
|
ht_sig_stb <= 1;
|
||||||
|
pkt_ht <= 1;
|
||||||
|
if (crc_out ^ crc) begin
|
||||||
|
pkt_header_valid_strobe <= 1;
|
||||||
|
status_code <= E_WRONG_CRC;
|
||||||
state <= S_HT_SIG_ERROR;
|
state <= S_HT_SIG_ERROR;
|
||||||
end else begin
|
end else begin
|
||||||
`ifdef DEBUG_PRINT
|
`ifdef DEBUG_PRINT
|
||||||
$display("[HT SIGNAL] CRC OK");
|
$display("[HT SIGNAL] CRC OK");
|
||||||
`endif
|
`endif
|
||||||
ht_sig_crc_ok <= 1;
|
ht_sig_crc_ok <= 1;
|
||||||
ht_sig_stb <= 1;
|
|
||||||
ofdm_reset <= 1;
|
|
||||||
state <= S_CHECK_HT_SIG;
|
state <= S_CHECK_HT_SIG;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
S_CHECK_HT_SIG: begin
|
S_CHECK_HT_SIG: begin
|
||||||
ofdm_reset <= 0;
|
ofdm_reset <= 1;
|
||||||
ht_sig_stb <= 0;
|
ht_sig_stb <= 0;
|
||||||
|
|
||||||
|
pkt_header_valid <= 1;
|
||||||
|
pkt_header_valid_strobe <= 1;
|
||||||
if (ht_mcs > 7) begin
|
if (ht_mcs > 7) begin
|
||||||
|
ht_unsupport <= 1;
|
||||||
status_code <= E_UNSUPPORTED_MCS;
|
status_code <= E_UNSUPPORTED_MCS;
|
||||||
state <= S_HT_SIG_ERROR;
|
state <= S_HT_SIG_ERROR;
|
||||||
end else if (ht_cbw) begin
|
end else if (ht_cbw) begin
|
||||||
|
ht_unsupport <= 1;
|
||||||
status_code <= E_UNSUPPORTED_CBW;
|
status_code <= E_UNSUPPORTED_CBW;
|
||||||
state <= S_HT_SIG_ERROR;
|
state <= S_HT_SIG_ERROR;
|
||||||
end else if (ht_rsvd == 0) begin
|
end else if (ht_rsvd == 0) begin
|
||||||
|
ht_unsupport <= 1;
|
||||||
status_code <= E_HT_WRONG_RSVD;
|
status_code <= E_HT_WRONG_RSVD;
|
||||||
state <= S_HT_SIG_ERROR;
|
state <= S_HT_SIG_ERROR;
|
||||||
end else if (ht_stbc != 0) begin
|
end else if (ht_stbc != 0) begin
|
||||||
|
ht_unsupport <= 1;
|
||||||
status_code <= E_UNSUPPORTED_STBC;
|
status_code <= E_UNSUPPORTED_STBC;
|
||||||
state <= S_HT_SIG_ERROR;
|
state <= S_HT_SIG_ERROR;
|
||||||
end else if (ht_fec_coding) begin
|
end else if (ht_fec_coding) begin
|
||||||
|
ht_unsupport <= 1;
|
||||||
status_code <= E_UNSUPPORTED_FEC;
|
status_code <= E_UNSUPPORTED_FEC;
|
||||||
state <= S_HT_SIG_ERROR;
|
state <= S_HT_SIG_ERROR;
|
||||||
end else if (short_gi) begin
|
// end else if (ht_sgi) begin // seems like it supports ht short_gi, we should proceed
|
||||||
status_code <= E_UNSUPPORTED_SGI;
|
// ht_unsupport <= 1;
|
||||||
state <= S_HT_SIG_ERROR;
|
// status_code <= E_UNSUPPORTED_SGI;
|
||||||
|
// state <= S_HT_SIG_ERROR;
|
||||||
end else if (ht_num_ext != 0) begin
|
end else if (ht_num_ext != 0) begin
|
||||||
|
ht_unsupport <= 1;
|
||||||
status_code <= E_UNSUPPORTED_SPATIAL;
|
status_code <= E_UNSUPPORTED_SPATIAL;
|
||||||
state <= S_HT_SIG_ERROR;
|
state <= S_HT_SIG_ERROR;
|
||||||
end else if (ht_sig_tail != 0) begin
|
end else if (ht_sig_tail != 0) begin
|
||||||
|
ht_unsupport <= 1;
|
||||||
status_code <= E_HT_WRONG_TAIL;
|
status_code <= E_HT_WRONG_TAIL;
|
||||||
state <= S_HT_SIG_ERROR;
|
state <= S_HT_SIG_ERROR;
|
||||||
end else begin
|
end else begin
|
||||||
@ -764,11 +784,18 @@ always @(posedge clock) begin
|
|||||||
end
|
end
|
||||||
|
|
||||||
S_HT_SIG_ERROR: begin
|
S_HT_SIG_ERROR: begin
|
||||||
|
ht_unsupport <= 0;
|
||||||
|
pkt_header_valid <= 0;
|
||||||
|
pkt_header_valid_strobe <= 0;
|
||||||
|
byte_count <= 0;
|
||||||
|
byte_count_total <= 0;
|
||||||
ht_sig_stb <= 0;
|
ht_sig_stb <= 0;
|
||||||
state <= S_WAIT_POWER_TRIGGER;
|
state <= S_WAIT_POWER_TRIGGER;
|
||||||
end
|
end
|
||||||
|
|
||||||
S_HT_STS: begin
|
S_HT_STS: begin
|
||||||
|
pkt_header_valid <= 0;
|
||||||
|
pkt_header_valid_strobe <= 0;
|
||||||
if (sync_long_out_strobe) begin
|
if (sync_long_out_strobe) begin
|
||||||
sync_long_out_count <= sync_long_out_count + 1;
|
sync_long_out_count <= sync_long_out_count + 1;
|
||||||
end
|
end
|
||||||
@ -786,14 +813,10 @@ always @(posedge clock) begin
|
|||||||
end
|
end
|
||||||
if (sync_long_out_count == 64) begin
|
if (sync_long_out_count == 64) begin
|
||||||
ht_next <= 0;
|
ht_next <= 0;
|
||||||
num_bits_to_decode <= (ht_len+3)<<4;
|
//num_bits_to_decode <= (ht_len+3)<<4;
|
||||||
pkt_rate <= {1'b1, ht_mcs};
|
|
||||||
do_descramble <= 1;
|
do_descramble <= 1;
|
||||||
ofdm_reset <= 1;
|
ofdm_reset <= 1;
|
||||||
byte_count <= 0;
|
|
||||||
pkt_len <= ht_len;
|
|
||||||
pkt_begin <= 1;
|
pkt_begin <= 1;
|
||||||
pkt_ht <= 1;
|
|
||||||
state <= S_DECODE_DATA;
|
state <= S_DECODE_DATA;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
@ -802,9 +825,10 @@ always @(posedge clock) begin
|
|||||||
pkt_begin <= 0;
|
pkt_begin <= 0;
|
||||||
legacy_sig_stb <= 0;
|
legacy_sig_stb <= 0;
|
||||||
|
|
||||||
if (ofdm_reset) begin
|
pkt_header_valid <= 0;
|
||||||
|
pkt_header_valid_strobe <= 0;
|
||||||
|
|
||||||
ofdm_reset <= 0;
|
ofdm_reset <= 0;
|
||||||
end
|
|
||||||
|
|
||||||
ofdm_in_stb <= eq_out_stb_delayed;
|
ofdm_in_stb <= eq_out_stb_delayed;
|
||||||
ofdm_in_i <= eq_out_i_delayed;
|
ofdm_in_i <= eq_out_i_delayed;
|
||||||
@ -816,10 +840,13 @@ always @(posedge clock) begin
|
|||||||
byte_out);
|
byte_out);
|
||||||
`endif
|
`endif
|
||||||
byte_count <= byte_count + 1;
|
byte_count <= byte_count + 1;
|
||||||
|
byte_count_total <= byte_count_total + 1;
|
||||||
end
|
end
|
||||||
|
|
||||||
if (byte_count >= pkt_len) begin
|
if (byte_count >= pkt_len) begin
|
||||||
fcs_out_strobe <= 1;
|
fcs_out_strobe <= 1;
|
||||||
|
byte_count <= 0;
|
||||||
|
byte_count_total <= 0;
|
||||||
if (pkt_fcs == EXPECTED_FCS) begin
|
if (pkt_fcs == EXPECTED_FCS) begin
|
||||||
fcs_ok <= 1;
|
fcs_ok <= 1;
|
||||||
status_code <= E_OK;
|
status_code <= E_OK;
|
||||||
@ -846,6 +873,8 @@ always @(posedge clock) begin
|
|||||||
end
|
end
|
||||||
|
|
||||||
default: begin
|
default: begin
|
||||||
|
byte_count <= 0;
|
||||||
|
byte_count_total <= 0;
|
||||||
state <= S_WAIT_POWER_TRIGGER;
|
state <= S_WAIT_POWER_TRIGGER;
|
||||||
end
|
end
|
||||||
endcase
|
endcase
|
||||||
|
@ -7,6 +7,7 @@ reg clock;
|
|||||||
reg reset;
|
reg reset;
|
||||||
reg enable;
|
reg enable;
|
||||||
|
|
||||||
|
reg [10:0] rssi_half_db;
|
||||||
reg[31:0] sample_in;
|
reg[31:0] sample_in;
|
||||||
reg sample_in_strobe;
|
reg sample_in_strobe;
|
||||||
reg [15:0] clk_count;
|
reg [15:0] clk_count;
|
||||||
@ -28,8 +29,8 @@ wire equalizer_out_strobe;
|
|||||||
wire [5:0] demod_out;
|
wire [5:0] demod_out;
|
||||||
wire demod_out_strobe;
|
wire demod_out_strobe;
|
||||||
|
|
||||||
wire [1:0] deinterleave_out;
|
wire [3:0] deinterleave_erase_out;
|
||||||
wire deinterleave_out_strobe;
|
wire deinterleave_erase_out_strobe;
|
||||||
|
|
||||||
wire conv_decoder_out;
|
wire conv_decoder_out;
|
||||||
wire conv_decoder_out_stb;
|
wire conv_decoder_out_stb;
|
||||||
@ -40,33 +41,30 @@ wire descramble_out_strobe;
|
|||||||
wire [3:0] legacy_rate;
|
wire [3:0] legacy_rate;
|
||||||
wire legacy_sig_rsvd;
|
wire legacy_sig_rsvd;
|
||||||
wire [11:0] legacy_len;
|
wire [11:0] legacy_len;
|
||||||
wire legacy_sig_parity, legacy_sig_parity_ok;
|
wire legacy_sig_parity;
|
||||||
wire [5:0] legacy_sig_tail;
|
wire [5:0] legacy_sig_tail;
|
||||||
wire legacy_sig_stb;
|
wire legacy_sig_stb;
|
||||||
wire [23:0] sig_bits_spy;
|
|
||||||
wire [31:0] byte_count_spy;
|
|
||||||
reg signal_done;
|
reg signal_done;
|
||||||
|
|
||||||
wire [3:0] dot11_state;
|
wire [3:0] dot11_state;
|
||||||
|
|
||||||
|
wire pkt_header_valid_strobe;
|
||||||
wire [7:0] byte_out;
|
wire [7:0] byte_out;
|
||||||
wire byte_out_strobe;
|
wire byte_out_strobe;
|
||||||
|
wire [15:0] byte_count_total;
|
||||||
wire [63:0] data_out ;
|
wire [15:0] byte_count;
|
||||||
wire data_out_valid ;
|
wire [15:0] pkt_len_total;
|
||||||
|
wire [15:0] pkt_len;
|
||||||
|
wire [63:0] word_out;
|
||||||
|
wire word_out_strobe;
|
||||||
|
|
||||||
reg set_stb;
|
reg set_stb;
|
||||||
reg [7:0] set_addr;
|
reg [7:0] set_addr;
|
||||||
reg [31:0] set_data;
|
reg [31:0] set_data;
|
||||||
|
|
||||||
|
|
||||||
wire fcs_out_strobe, fcs_ok;
|
wire fcs_out_strobe, fcs_ok;
|
||||||
|
|
||||||
localparam RAM_SIZE = 1<<25;
|
integer addr;
|
||||||
|
|
||||||
reg [31:0] ram [0:RAM_SIZE-1];
|
|
||||||
reg [31:0] addr;
|
|
||||||
|
|
||||||
integer bb_sample_fd;
|
integer bb_sample_fd;
|
||||||
integer power_trigger_fd;
|
integer power_trigger_fd;
|
||||||
@ -79,7 +77,7 @@ integer sync_long_out_fd;
|
|||||||
integer equalizer_out_fd;
|
integer equalizer_out_fd;
|
||||||
|
|
||||||
integer demod_out_fd;
|
integer demod_out_fd;
|
||||||
integer deinterleave_out_fd;
|
integer deinterleave_erase_out_fd;
|
||||||
integer conv_out_fd;
|
integer conv_out_fd;
|
||||||
integer descramble_out_fd;
|
integer descramble_out_fd;
|
||||||
|
|
||||||
@ -87,28 +85,18 @@ integer signal_fd;
|
|||||||
|
|
||||||
integer byte_out_fd;
|
integer byte_out_fd;
|
||||||
|
|
||||||
integer fcs_fd ;
|
|
||||||
|
|
||||||
// spy ports added (lwei)
|
|
||||||
wire [1:0] pw_state_spy;
|
|
||||||
|
|
||||||
`ifndef SAMPLE_FILE
|
integer file_i, file_q, file_rssi_half_db, iq_sample_file;
|
||||||
`define SAMPLE_FILE "../testing_inputs/conducted/dot11a_24mbps_qos_data_e4_90_7e_15_2a_16_e8_de_27_90_6e_42.txt"
|
|
||||||
`endif
|
|
||||||
|
|
||||||
`ifndef NUM_SAMPLE
|
//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_65mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
|
||||||
`define NUM_SAMPLE 3000
|
`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11a_48mbps_qos_data_e4_90_7e_15_2a_16_e8_de_27_90_6e_42_openwifi.txt"
|
||||||
`endif
|
`define NUM_SAMPLE 4560
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
$dumpfile("dot11.vcd");
|
$dumpfile("dot11.vcd");
|
||||||
$dumpvars;
|
$dumpvars;
|
||||||
|
|
||||||
$display("Reading memory from...");
|
|
||||||
$display(`SAMPLE_FILE);
|
|
||||||
$readmemh(`SAMPLE_FILE, ram);
|
|
||||||
$display("Done.");
|
|
||||||
|
|
||||||
clock = 0;
|
clock = 0;
|
||||||
reset = 1;
|
reset = 1;
|
||||||
enable = 0;
|
enable = 0;
|
||||||
@ -126,32 +114,31 @@ initial begin
|
|||||||
|
|
||||||
# 20 set_stb = 0;
|
# 20 set_stb = 0;
|
||||||
|
|
||||||
bb_sample_fd = $fopen("./sim_out/sample_in.txt", "w");
|
iq_sample_file = $fopen(`SAMPLE_FILE, "r");
|
||||||
power_trigger_fd = $fopen("./sim_out/power_trigger.txt", "w");
|
|
||||||
short_preamble_detected_fd = $fopen("./sim_out/short_preamble_detected.txt", "w");
|
|
||||||
|
|
||||||
sync_long_metric_fd = $fopen("./sim_out/sync_long_metric.txt", "w");
|
bb_sample_fd = $fopen("./sample_in.txt", "w");
|
||||||
long_preamble_detected_fd = $fopen("./sim_out/sync_long_frame_detected.txt", "w");
|
power_trigger_fd = $fopen("./power_trigger.txt", "w");
|
||||||
sync_long_out_fd = $fopen("./sim_out/sync_long_out.txt", "w");
|
short_preamble_detected_fd = $fopen("./short_preamble_detected.txt", "w");
|
||||||
|
|
||||||
equalizer_out_fd = $fopen("./sim_out/equalizer_out.txt", "w");
|
sync_long_metric_fd = $fopen("./sync_long_metric.txt", "w");
|
||||||
|
long_preamble_detected_fd = $fopen("./sync_long_frame_detected.txt", "w");
|
||||||
|
sync_long_out_fd = $fopen("./sync_long_out.txt", "w");
|
||||||
|
|
||||||
demod_out_fd = $fopen("./sim_out/demod_out.txt", "w");
|
equalizer_out_fd = $fopen("./equalizer_out.txt", "w");
|
||||||
deinterleave_out_fd = $fopen("./sim_out/deinterleave_out.txt", "w");
|
|
||||||
conv_out_fd = $fopen("./sim_out/conv_out.txt", "w");
|
|
||||||
descramble_out_fd = $fopen("./sim_out/descramble_out.txt", "w");
|
|
||||||
|
|
||||||
signal_fd = $fopen("./sim_out/signal_out.txt", "w");
|
demod_out_fd = $fopen("./demod_out.txt", "w");
|
||||||
|
deinterleave_erase_out_fd = $fopen("./deinterleave_erase_out.txt", "w");
|
||||||
|
conv_out_fd = $fopen("./conv_out.txt", "w");
|
||||||
|
descramble_out_fd = $fopen("./descramble_out.txt", "w");
|
||||||
|
|
||||||
byte_out_fd = $fopen("./sim_out/byte_out.txt", "w");
|
signal_fd = $fopen("./signal_out.txt", "w");
|
||||||
|
|
||||||
fcs_fd = $fopen("./sim_out/fcs_out.txt", "w");
|
byte_out_fd = $fopen("./byte_out.txt", "w");
|
||||||
//# 50100; enable = 0 ;
|
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
||||||
always begin
|
always begin //200MHz
|
||||||
#5 clock = !clock;
|
#2.5 clock = !clock;
|
||||||
end
|
end
|
||||||
|
|
||||||
always @(posedge clock) begin
|
always @(posedge clock) begin
|
||||||
@ -161,9 +148,12 @@ always @(posedge clock) begin
|
|||||||
sample_in_strobe <= 0;
|
sample_in_strobe <= 0;
|
||||||
addr <= 0;
|
addr <= 0;
|
||||||
end else if (enable) begin
|
end else if (enable) begin
|
||||||
if (clk_count == 4) begin
|
if (clk_count == 9) begin
|
||||||
sample_in_strobe <= 1;
|
sample_in_strobe <= 1;
|
||||||
sample_in <= ram[addr];
|
$fscanf(iq_sample_file, "%d %d %d", file_i, file_q, file_rssi_half_db);
|
||||||
|
sample_in[15:0] <= file_q;
|
||||||
|
sample_in[31:16]<= file_i;
|
||||||
|
rssi_half_db <= file_rssi_half_db;
|
||||||
addr <= addr + 1;
|
addr <= addr + 1;
|
||||||
clk_count <= 0;
|
clk_count <= 0;
|
||||||
end else begin
|
end else begin
|
||||||
@ -174,7 +164,8 @@ always @(posedge clock) begin
|
|||||||
if (legacy_sig_stb) begin
|
if (legacy_sig_stb) begin
|
||||||
end
|
end
|
||||||
|
|
||||||
if (sample_in_strobe && power_trigger) begin
|
//if (sample_in_strobe && power_trigger) begin
|
||||||
|
if (sample_in_strobe) begin
|
||||||
$fwrite(bb_sample_fd, "%d %d %d\n", $time/2, $signed(sample_in[31:16]), $signed(sample_in[15:0]));
|
$fwrite(bb_sample_fd, "%d %d %d\n", $time/2, $signed(sample_in[31:16]), $signed(sample_in[15:0]));
|
||||||
$fwrite(power_trigger_fd, "%d %d\n", $time/2, power_trigger);
|
$fwrite(power_trigger_fd, "%d %d\n", $time/2, power_trigger);
|
||||||
$fwrite(short_preamble_detected_fd, "%d %d\n", $time/2, short_preamble_detected);
|
$fwrite(short_preamble_detected_fd, "%d %d\n", $time/2, short_preamble_detected);
|
||||||
@ -184,22 +175,41 @@ always @(posedge clock) begin
|
|||||||
$fflush(bb_sample_fd);
|
$fflush(bb_sample_fd);
|
||||||
$fflush(power_trigger_fd);
|
$fflush(power_trigger_fd);
|
||||||
$fflush(short_preamble_detected_fd);
|
$fflush(short_preamble_detected_fd);
|
||||||
|
|
||||||
$fflush(sync_long_metric_fd);
|
|
||||||
$fflush(long_preamble_detected_fd);
|
$fflush(long_preamble_detected_fd);
|
||||||
|
|
||||||
|
|
||||||
if ((addr % 100) == 0) begin
|
if ((addr % 100) == 0) begin
|
||||||
$display("%d / %d", addr, RAM_SIZE);
|
$display("%d", addr);
|
||||||
end
|
end
|
||||||
|
|
||||||
if (addr == `NUM_SAMPLE) begin
|
if (addr == `NUM_SAMPLE) begin
|
||||||
|
$fclose(iq_sample_file);
|
||||||
|
|
||||||
|
$fclose(bb_sample_fd);
|
||||||
|
$fclose(power_trigger_fd);
|
||||||
|
$fclose(short_preamble_detected_fd);
|
||||||
|
|
||||||
|
$fclose(sync_long_metric_fd);
|
||||||
|
$fclose(long_preamble_detected_fd);
|
||||||
|
$fclose(sync_long_out_fd);
|
||||||
|
|
||||||
|
$fclose(equalizer_out_fd);
|
||||||
|
|
||||||
|
$fclose(demod_out_fd);
|
||||||
|
$fclose(deinterleave_erase_out_fd);
|
||||||
|
$fclose(conv_out_fd);
|
||||||
|
$fclose(descramble_out_fd);
|
||||||
|
|
||||||
|
$fclose(signal_fd);
|
||||||
|
$fclose(byte_out_fd);
|
||||||
|
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
if (sync_long_metric_stb) begin
|
if (sync_long_metric_stb) begin
|
||||||
$fwrite(sync_long_metric_fd, "%d %d\n", $time/2, sync_long_metric);
|
$fwrite(sync_long_metric_fd, "%d %d\n", $time/2, sync_long_metric);
|
||||||
|
$fflush(sync_long_metric_fd);
|
||||||
end
|
end
|
||||||
|
|
||||||
if (sync_long_out_strobe) begin
|
if (sync_long_out_strobe) begin
|
||||||
@ -219,13 +229,13 @@ always @(posedge clock) begin
|
|||||||
end
|
end
|
||||||
|
|
||||||
if (dot11_state == S_DECODE_DATA && demod_out_strobe) begin
|
if (dot11_state == S_DECODE_DATA && demod_out_strobe) begin
|
||||||
$fwrite(demod_out_fd, "%06b\n", demod_out);
|
$fwrite(demod_out_fd, "%b %b %b %b %b %b\n",demod_out[0],demod_out[1],demod_out[2],demod_out[3],demod_out[4],demod_out[5]);
|
||||||
$fflush(demod_out_fd);
|
$fflush(demod_out_fd);
|
||||||
end
|
end
|
||||||
|
|
||||||
if (dot11_state == S_DECODE_DATA && deinterleave_out_strobe) begin
|
if (dot11_state == S_DECODE_DATA && deinterleave_erase_out_strobe) begin
|
||||||
$fwrite(deinterleave_out_fd, "%b%b\n", deinterleave_out[0], deinterleave_out[1]);
|
$fwrite(deinterleave_erase_out_fd, "%b %b %b %b\n", deinterleave_erase_out[0], deinterleave_erase_out[1], deinterleave_erase_out[2], deinterleave_erase_out[3]);
|
||||||
$fflush(deinterleave_out_fd);
|
$fflush(deinterleave_erase_out_fd);
|
||||||
end
|
end
|
||||||
|
|
||||||
if (dot11_state == S_DECODE_DATA && conv_decoder_out_stb) begin
|
if (dot11_state == S_DECODE_DATA && conv_decoder_out_stb) begin
|
||||||
@ -243,11 +253,6 @@ always @(posedge clock) begin
|
|||||||
$fflush(byte_out_fd);
|
$fflush(byte_out_fd);
|
||||||
end
|
end
|
||||||
|
|
||||||
if (fcs_out_strobe) begin
|
|
||||||
$fwrite(fcs_fd, "%d\n", fcs_ok);
|
|
||||||
$fflush(fcs_fd);
|
|
||||||
end
|
|
||||||
|
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
@ -255,20 +260,21 @@ dot11 dot11_inst (
|
|||||||
.clock(clock),
|
.clock(clock),
|
||||||
.reset(reset),
|
.reset(reset),
|
||||||
.enable(enable),
|
.enable(enable),
|
||||||
|
|
||||||
|
//.set_stb(set_stb),
|
||||||
|
//.set_addr(set_addr),
|
||||||
|
//.set_data(set_data),
|
||||||
|
|
||||||
|
.power_thres(11'd0),
|
||||||
|
.min_plateau(32'd100),
|
||||||
|
|
||||||
|
.rssi_half_db(rssi_half_db),
|
||||||
.sample_in(sample_in),
|
.sample_in(sample_in),
|
||||||
.sample_in_strobe(sample_in_strobe),
|
.sample_in_strobe(sample_in_strobe),
|
||||||
//.set_addr(set_addr),
|
|
||||||
//.set_stb(set_stb),
|
|
||||||
//.set_data(set_data),
|
|
||||||
.power_thres(16'd100),
|
|
||||||
.window_size(16'd80),
|
|
||||||
.num_sample_to_skip(32'd10),
|
|
||||||
.num_sample_changed(1'b0),
|
|
||||||
.min_plateau(32'd100),
|
|
||||||
.state(dot11_state),
|
.state(dot11_state),
|
||||||
|
|
||||||
.power_trigger(power_trigger),
|
.power_trigger(power_trigger),
|
||||||
.pw_state_spy(pw_state_spy),
|
|
||||||
.short_preamble_detected(short_preamble_detected),
|
.short_preamble_detected(short_preamble_detected),
|
||||||
|
|
||||||
.sync_long_metric(sync_long_metric),
|
.sync_long_metric(sync_long_metric),
|
||||||
@ -284,8 +290,8 @@ dot11 dot11_inst (
|
|||||||
.demod_out(demod_out),
|
.demod_out(demod_out),
|
||||||
.demod_out_strobe(demod_out_strobe),
|
.demod_out_strobe(demod_out_strobe),
|
||||||
|
|
||||||
.deinterleave_out(deinterleave_out),
|
.deinterleave_erase_out(deinterleave_erase_out),
|
||||||
.deinterleave_out_strobe(deinterleave_out_strobe),
|
.deinterleave_erase_out_strobe(deinterleave_erase_out_strobe),
|
||||||
|
|
||||||
.conv_decoder_out(conv_decoder_out),
|
.conv_decoder_out(conv_decoder_out),
|
||||||
.conv_decoder_out_stb(conv_decoder_out_stb),
|
.conv_decoder_out_stb(conv_decoder_out_stb),
|
||||||
@ -293,24 +299,37 @@ dot11 dot11_inst (
|
|||||||
.descramble_out(descramble_out),
|
.descramble_out(descramble_out),
|
||||||
.descramble_out_strobe(descramble_out_strobe),
|
.descramble_out_strobe(descramble_out_strobe),
|
||||||
|
|
||||||
|
.pkt_header_valid_strobe(pkt_header_valid_strobe),
|
||||||
.byte_out(byte_out),
|
.byte_out(byte_out),
|
||||||
.byte_out_strobe(byte_out_strobe),
|
.byte_out_strobe(byte_out_strobe),
|
||||||
|
.fcs_out_strobe(fcs_out_strobe),
|
||||||
.data_out(data_out),
|
.fcs_ok(fcs_ok),
|
||||||
.data_out_valid(data_out_valid),
|
.byte_count_total(byte_count_total),
|
||||||
|
.byte_count(byte_count),
|
||||||
|
.pkt_len_total(pkt_len_total),
|
||||||
|
.pkt_len(pkt_len),
|
||||||
|
|
||||||
.legacy_rate(legacy_rate),
|
.legacy_rate(legacy_rate),
|
||||||
.legacy_sig_rsvd(legacy_sig_rsvd),
|
.legacy_sig_rsvd(legacy_sig_rsvd),
|
||||||
.legacy_len(legacy_len),
|
.legacy_len(legacy_len),
|
||||||
.legacy_sig_parity(legacy_sig_parity),
|
.legacy_sig_parity(legacy_sig_parity),
|
||||||
.legacy_sig_parity_ok(legacy_sig_parity_ok),
|
|
||||||
.legacy_sig_tail(legacy_sig_tail),
|
.legacy_sig_tail(legacy_sig_tail),
|
||||||
.legacy_sig_stb(legacy_sig_stb),
|
.legacy_sig_stb(legacy_sig_stb)
|
||||||
.sig_bits_spy(sig_bits_spy),
|
|
||||||
.byte_count_spy(byte_count_spy),
|
|
||||||
|
|
||||||
.fcs_out_strobe(fcs_out_strobe),
|
|
||||||
.fcs_ok(fcs_ok)
|
|
||||||
);
|
);
|
||||||
|
|
||||||
|
byte_to_word_fcs_sn_insert byte_to_word_fcs_sn_insert_inst (
|
||||||
|
.clk(clock),
|
||||||
|
.rstn((~reset)&(~pkt_header_valid_strobe)),
|
||||||
|
|
||||||
|
.byte_in(byte_out),
|
||||||
|
.byte_in_strobe(byte_out_strobe),
|
||||||
|
.byte_count(byte_count),
|
||||||
|
.num_byte(pkt_len),
|
||||||
|
.fcs_in_strobe(fcs_out_strobe),
|
||||||
|
.fcs_ok(fcs_ok),
|
||||||
|
.rx_pkt_sn_plus_one(0),
|
||||||
|
|
||||||
|
.word_out(word_out),
|
||||||
|
.word_out_strobe(word_out_strobe)
|
||||||
|
);
|
||||||
endmodule
|
endmodule
|
||||||
|
@ -1,132 +0,0 @@
|
|||||||
|
|
||||||
`timescale 1 ns / 1 ps
|
|
||||||
|
|
||||||
module dot11zynq #
|
|
||||||
(
|
|
||||||
// Users to add parameters here
|
|
||||||
|
|
||||||
// User parameters ends
|
|
||||||
// Do not modify the parameters beyond this line
|
|
||||||
|
|
||||||
|
|
||||||
// Parameters of Axi Slave Bus Interface S00_AXI
|
|
||||||
parameter integer C_S00_AXI_DATA_WIDTH = 32,
|
|
||||||
parameter integer C_S00_AXI_ADDR_WIDTH = 7
|
|
||||||
)
|
|
||||||
(
|
|
||||||
// Users to add ports here
|
|
||||||
|
|
||||||
// User ports ends
|
|
||||||
// Do not modify the ports beyond this line
|
|
||||||
input wire enable,
|
|
||||||
input wire [31:0] sample_in,
|
|
||||||
input wire sample_in_strobe,
|
|
||||||
output wire trigger,
|
|
||||||
|
|
||||||
output wire ofdm_byte_valid,
|
|
||||||
output wire [7:0] ofdm_byte,
|
|
||||||
output wire [63:0] data_out,
|
|
||||||
output wire data_out_valid,
|
|
||||||
output wire fcs_valid,
|
|
||||||
output wire fcs_invalid,
|
|
||||||
|
|
||||||
output wire sig_valid,
|
|
||||||
output wire sig_invalid,
|
|
||||||
output wire [2:0] mcs_io,
|
|
||||||
output wire [11:0] pkt_len_io,
|
|
||||||
|
|
||||||
output wire [6:0] ht_mcs_io,
|
|
||||||
output wire [15:0] ht_pkt_len_io,
|
|
||||||
output wire ht_sig_invalid,
|
|
||||||
output wire ht_sig_valid,
|
|
||||||
output wire ht_unsupported,
|
|
||||||
|
|
||||||
|
|
||||||
// ports to interract with fifo
|
|
||||||
input wire fifo_empty,
|
|
||||||
output wire rd_en,
|
|
||||||
output wire fifo_rst,
|
|
||||||
// Ports of Axi Slave Bus Interface S00_AXI
|
|
||||||
input wire s00_axi_aclk,
|
|
||||||
input wire s00_axi_aresetn,
|
|
||||||
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
|
|
||||||
input wire [2 : 0] s00_axi_awprot,
|
|
||||||
input wire s00_axi_awvalid,
|
|
||||||
output wire s00_axi_awready,
|
|
||||||
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
|
|
||||||
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
|
|
||||||
input wire s00_axi_wvalid,
|
|
||||||
output wire s00_axi_wready,
|
|
||||||
output wire [1 : 0] s00_axi_bresp,
|
|
||||||
output wire s00_axi_bvalid,
|
|
||||||
input wire s00_axi_bready,
|
|
||||||
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
|
|
||||||
input wire [2 : 0] s00_axi_arprot,
|
|
||||||
input wire s00_axi_arvalid,
|
|
||||||
output wire s00_axi_arready,
|
|
||||||
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
|
|
||||||
output wire [1 : 0] s00_axi_rresp,
|
|
||||||
output wire s00_axi_rvalid,
|
|
||||||
input wire s00_axi_rready
|
|
||||||
);
|
|
||||||
// Instantiation of Axi Bus Interface S00_AXI
|
|
||||||
dot11zynq_S00_AXI # (
|
|
||||||
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
|
|
||||||
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
|
|
||||||
) dot11zynq_S00_AXI_inst (
|
|
||||||
// user ports
|
|
||||||
.enable(enable),
|
|
||||||
.sample_in(sample_in),
|
|
||||||
.sample_in_strobe(sample_in_strobe),
|
|
||||||
.trigger(trigger),
|
|
||||||
|
|
||||||
.ofdm_byte_valid(ofdm_byte_valid),
|
|
||||||
.ofdm_byte(ofdm_byte),
|
|
||||||
.data_out(data_out),
|
|
||||||
.data_out_valid(data_out_valid),
|
|
||||||
.fcs_valid(fcs_valid),
|
|
||||||
.fcs_invalid(fcs_invalid),
|
|
||||||
|
|
||||||
.sig_valid(sig_valid),
|
|
||||||
.sig_invalid(sig_invalid),
|
|
||||||
.mcs_io(mcs_io),
|
|
||||||
.pkt_len_io(pkt_len_io),
|
|
||||||
|
|
||||||
.ht_mcs_io(ht_mcs_io),
|
|
||||||
.ht_pkt_len_io(ht_pkt_len_io),
|
|
||||||
.ht_sig_invalid(ht_sig_invalid),
|
|
||||||
.ht_sig_valid(ht_sig_valid),
|
|
||||||
.ht_unsupported(ht_unsupported),
|
|
||||||
|
|
||||||
.fifo_empty(fifo_empty),
|
|
||||||
.rd_en(rd_en),
|
|
||||||
.fifo_rst(fifo_rst),
|
|
||||||
// user ports end
|
|
||||||
.S_AXI_ACLK(s00_axi_aclk),
|
|
||||||
.S_AXI_ARESETN(s00_axi_aresetn),
|
|
||||||
.S_AXI_AWADDR(s00_axi_awaddr),
|
|
||||||
.S_AXI_AWPROT(s00_axi_awprot),
|
|
||||||
.S_AXI_AWVALID(s00_axi_awvalid),
|
|
||||||
.S_AXI_AWREADY(s00_axi_awready),
|
|
||||||
.S_AXI_WDATA(s00_axi_wdata),
|
|
||||||
.S_AXI_WSTRB(s00_axi_wstrb),
|
|
||||||
.S_AXI_WVALID(s00_axi_wvalid),
|
|
||||||
.S_AXI_WREADY(s00_axi_wready),
|
|
||||||
.S_AXI_BRESP(s00_axi_bresp),
|
|
||||||
.S_AXI_BVALID(s00_axi_bvalid),
|
|
||||||
.S_AXI_BREADY(s00_axi_bready),
|
|
||||||
.S_AXI_ARADDR(s00_axi_araddr),
|
|
||||||
.S_AXI_ARPROT(s00_axi_arprot),
|
|
||||||
.S_AXI_ARVALID(s00_axi_arvalid),
|
|
||||||
.S_AXI_ARREADY(s00_axi_arready),
|
|
||||||
.S_AXI_RDATA(s00_axi_rdata),
|
|
||||||
.S_AXI_RRESP(s00_axi_rresp),
|
|
||||||
.S_AXI_RVALID(s00_axi_rvalid),
|
|
||||||
.S_AXI_RREADY(s00_axi_rready)
|
|
||||||
);
|
|
||||||
|
|
||||||
// Add user logic here
|
|
||||||
|
|
||||||
// User logic ends
|
|
||||||
|
|
||||||
endmodule
|
|
@ -22,7 +22,7 @@ module equalizer
|
|||||||
output reg [31:0] sample_out,
|
output reg [31:0] sample_out,
|
||||||
output reg sample_out_strobe,
|
output reg sample_out_strobe,
|
||||||
|
|
||||||
output reg [2:0] state
|
(* mark_debug = "true" *) output reg [2:0] state
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
@ -122,8 +122,8 @@ wire signed [15:0] rot_q;
|
|||||||
wire [31:0] mag_sq;
|
wire [31:0] mag_sq;
|
||||||
wire [31:0] prod_i;
|
wire [31:0] prod_i;
|
||||||
wire [31:0] prod_q;
|
wire [31:0] prod_q;
|
||||||
wire [31:0] prod_i_scaled = prod_i<<`CONS_SCALE_SHIFT;
|
wire [31:0] prod_i_scaled = prod_i<<(`CONS_SCALE_SHIFT+1);
|
||||||
wire [31:0] prod_q_scaled = prod_q<<`CONS_SCALE_SHIFT;
|
wire [31:0] prod_q_scaled = prod_q<<(`CONS_SCALE_SHIFT+1); // +1 to fix the bug threshold for demodulate.v
|
||||||
wire prod_stb;
|
wire prod_stb;
|
||||||
|
|
||||||
reg [15:0] num_output;
|
reg [15:0] num_output;
|
||||||
|
125
verilog/last_sym_indicator.v
Normal file
125
verilog/last_sym_indicator.v
Normal file
@ -0,0 +1,125 @@
|
|||||||
|
/*
|
||||||
|
* track ofdm symbol and give indication of end of all ofdm symbol
|
||||||
|
*/
|
||||||
|
module last_sym_indicator
|
||||||
|
(
|
||||||
|
input clock,
|
||||||
|
input reset,
|
||||||
|
input enable,
|
||||||
|
|
||||||
|
input ofdm_sym_valid,
|
||||||
|
input [7:0] pkt_rate,//bit [7] 1 means ht; 0 means non-ht
|
||||||
|
input [15:0] pkt_len,
|
||||||
|
input ht_correction,
|
||||||
|
|
||||||
|
output reg last_sym_flag
|
||||||
|
);
|
||||||
|
|
||||||
|
localparam S_WAIT_FOR_ALL_SYM = 0;
|
||||||
|
localparam S_ALL_SYM_RECEIVED = 1;
|
||||||
|
|
||||||
|
reg state;
|
||||||
|
reg ofdm_sym_valid_reg;
|
||||||
|
|
||||||
|
reg [8:0] n_dbps;
|
||||||
|
reg [7:0] n_ofdm_sym;
|
||||||
|
wire [16:0] n_bit;
|
||||||
|
wire [16:0] n_bit_target;
|
||||||
|
|
||||||
|
assign n_bit = n_dbps*(n_ofdm_sym+ht_correction);
|
||||||
|
assign n_bit_target = (({1'b0,pkt_len}<<3) + 16 + 6);
|
||||||
|
|
||||||
|
// lookup table for N_DBPS (Number of data bits per OFDM symbol)
|
||||||
|
always @( pkt_rate[7],pkt_rate[3:0] )
|
||||||
|
begin
|
||||||
|
case ({pkt_rate[7],pkt_rate[3:0]})
|
||||||
|
5'b01011 : begin //non-ht 6Mbps
|
||||||
|
n_dbps = 24;
|
||||||
|
end
|
||||||
|
5'b01111 : begin //non-ht 9Mbps
|
||||||
|
n_dbps = 36;
|
||||||
|
end
|
||||||
|
5'b01010 : begin //non-ht 12Mbps
|
||||||
|
n_dbps = 48;
|
||||||
|
end
|
||||||
|
5'b01110 : begin //non-ht 18Mbps
|
||||||
|
n_dbps = 72;
|
||||||
|
end
|
||||||
|
5'b01001 : begin //non-ht 24Mbps
|
||||||
|
n_dbps = 96;
|
||||||
|
end
|
||||||
|
5'b01101 : begin //non-ht 36Mbps
|
||||||
|
n_dbps = 144;
|
||||||
|
end
|
||||||
|
5'b01000 : begin //non-ht 48Mbps
|
||||||
|
n_dbps = 192;
|
||||||
|
end
|
||||||
|
5'b01100 : begin //non-ht 54Mbps
|
||||||
|
n_dbps = 216;
|
||||||
|
end
|
||||||
|
5'b10000 : begin //ht mcs 0
|
||||||
|
n_dbps = 26;
|
||||||
|
end
|
||||||
|
5'b10001 : begin //ht mcs 1
|
||||||
|
n_dbps = 52;
|
||||||
|
end
|
||||||
|
5'b10010 : begin //ht mcs 2
|
||||||
|
n_dbps = 78;
|
||||||
|
end
|
||||||
|
5'b10011 : begin //ht mcs 3
|
||||||
|
n_dbps = 104;
|
||||||
|
end
|
||||||
|
5'b10100 : begin //ht mcs 4
|
||||||
|
n_dbps = 156;
|
||||||
|
end
|
||||||
|
5'b10101 : begin //ht mcs 5
|
||||||
|
n_dbps = 208;
|
||||||
|
end
|
||||||
|
5'b10110 : begin //ht mcs 6
|
||||||
|
n_dbps = 234;
|
||||||
|
end
|
||||||
|
5'b10111 : begin //ht mcs 7
|
||||||
|
n_dbps = 260;
|
||||||
|
end
|
||||||
|
default: begin
|
||||||
|
n_dbps = 0;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clock) begin
|
||||||
|
if (reset) begin
|
||||||
|
ofdm_sym_valid_reg <= 0;
|
||||||
|
end else begin
|
||||||
|
ofdm_sym_valid_reg <= ofdm_sym_valid;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clock) begin
|
||||||
|
if (reset) begin
|
||||||
|
n_ofdm_sym <= 0;
|
||||||
|
last_sym_flag <= 0;
|
||||||
|
state <= S_WAIT_FOR_ALL_SYM;
|
||||||
|
end else if (ofdm_sym_valid==0 && ofdm_sym_valid_reg==1) begin //falling edge means that current deinterleaving is finished, then we can start flush to speedup finishing work.
|
||||||
|
n_ofdm_sym <= n_ofdm_sym + 1;
|
||||||
|
if (enable) begin
|
||||||
|
case(state)
|
||||||
|
S_WAIT_FOR_ALL_SYM: begin
|
||||||
|
if ( (n_bit_target-n_bit)<=n_dbps ) begin
|
||||||
|
last_sym_flag <= 0;
|
||||||
|
state <= S_ALL_SYM_RECEIVED;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
S_ALL_SYM_RECEIVED: begin
|
||||||
|
last_sym_flag <= 1;
|
||||||
|
state <= S_ALL_SYM_RECEIVED;
|
||||||
|
end
|
||||||
|
default: begin
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
@ -12,17 +12,17 @@ module ofdm_decoder
|
|||||||
input do_descramble,
|
input do_descramble,
|
||||||
input [31:0] num_bits_to_decode,
|
input [31:0] num_bits_to_decode,
|
||||||
|
|
||||||
output [5:0] demod_out,
|
(* mark_debug = "false" *) output [5:0] demod_out,
|
||||||
output demod_out_strobe,
|
(* mark_debug = "false" *) output demod_out_strobe,
|
||||||
|
|
||||||
output [1:0] deinterleave_out,
|
(* mark_debug = "false" *) output [3:0] deinterleave_erase_out,
|
||||||
output deinterleave_out_strobe,
|
(* mark_debug = "false" *) output deinterleave_erase_out_strobe,
|
||||||
|
|
||||||
output conv_decoder_out,
|
(* mark_debug = "false" *) output conv_decoder_out,
|
||||||
output conv_decoder_out_stb,
|
(* mark_debug = "false" *) output conv_decoder_out_stb,
|
||||||
|
|
||||||
output descramble_out,
|
(* mark_debug = "false" *) output descramble_out,
|
||||||
output descramble_out_strobe,
|
(* mark_debug = "false" *) output descramble_out_strobe,
|
||||||
|
|
||||||
output [7:0] byte_out,
|
output [7:0] byte_out,
|
||||||
output byte_out_strobe
|
output byte_out_strobe
|
||||||
@ -37,11 +37,13 @@ wire [15:0] input_i = sample_in[31:16];
|
|||||||
wire [15:0] input_q = sample_in[15:0];
|
wire [15:0] input_q = sample_in[15:0];
|
||||||
|
|
||||||
wire vit_ce = reset | (enable & conv_in_stb) | conv_in_stb_dly;
|
wire vit_ce = reset | (enable & conv_in_stb) | conv_in_stb_dly;
|
||||||
|
//wire vit_ce = 1'b1 ;
|
||||||
wire vit_clr = reset;
|
wire vit_clr = reset;
|
||||||
reg vit_clr_dly;
|
reg vit_clr_dly;
|
||||||
wire vit_rdy;
|
wire vit_rdy;
|
||||||
|
|
||||||
|
wire [1:0] deinterleave_out;
|
||||||
|
wire deinterleave_out_strobe;
|
||||||
wire [1:0] erase;
|
wire [1:0] erase;
|
||||||
|
|
||||||
// assign conv_decoder_out_stb = vit_ce & vit_rdy;
|
// assign conv_decoder_out_stb = vit_ce & vit_rdy;
|
||||||
@ -51,8 +53,10 @@ reg bit_in;
|
|||||||
reg bit_in_stb;
|
reg bit_in_stb;
|
||||||
|
|
||||||
reg [31:0] deinter_out_count;
|
reg [31:0] deinter_out_count;
|
||||||
reg flush;
|
//reg flush;
|
||||||
|
|
||||||
|
assign deinterleave_erase_out = {erase,deinterleave_out};
|
||||||
|
assign deinterleave_erase_out_strobe = deinterleave_out_strobe;
|
||||||
demodulate demod_inst (
|
demodulate demod_inst (
|
||||||
.clock(clock),
|
.clock(clock),
|
||||||
.reset(reset),
|
.reset(reset),
|
||||||
@ -79,9 +83,21 @@ deinterleave deinterleave_inst (
|
|||||||
.output_strobe(deinterleave_out_strobe),
|
.output_strobe(deinterleave_out_strobe),
|
||||||
.erase(erase)
|
.erase(erase)
|
||||||
);
|
);
|
||||||
|
/*
|
||||||
|
viterbi_v7_0 viterbi_inst (
|
||||||
|
.clk(clock),
|
||||||
|
.ce(vit_ce),
|
||||||
|
.sclr(vit_clr),
|
||||||
|
.data_in0(conv_in0),
|
||||||
|
.data_in1(conv_in1),
|
||||||
|
.erase(conv_erase),
|
||||||
|
.rdy(vit_rdy),
|
||||||
|
.data_out(conv_decoder_out)
|
||||||
|
);
|
||||||
|
*/
|
||||||
wire m_axis_data_tvalid ;
|
wire m_axis_data_tvalid ;
|
||||||
|
//reg [4:0] idle_wire_5bit ;
|
||||||
|
//wire [6:0] idle_wire_7bit ;
|
||||||
viterbi_v7_0 viterbi_inst (
|
viterbi_v7_0 viterbi_inst (
|
||||||
.aclk(clock), // input wire aclk
|
.aclk(clock), // input wire aclk
|
||||||
.aresetn(~vit_clr), // input wire aresetn
|
.aresetn(~vit_clr), // input wire aresetn
|
||||||
@ -94,7 +110,6 @@ viterbi_v7_0 viterbi_inst (
|
|||||||
.m_axis_data_tvalid(m_axis_data_tvalid) // output wire m_axis_data_tvalid
|
.m_axis_data_tvalid(m_axis_data_tvalid) // output wire m_axis_data_tvalid
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
descramble decramble_inst (
|
descramble decramble_inst (
|
||||||
.clock(clock),
|
.clock(clock),
|
||||||
.enable(enable),
|
.enable(enable),
|
||||||
@ -132,20 +147,22 @@ always @(posedge clock) begin
|
|||||||
skip_bit <= 9;
|
skip_bit <= 9;
|
||||||
bit_in_stb <= 0;
|
bit_in_stb <= 0;
|
||||||
|
|
||||||
flush <= 0;
|
//flush <= 0;
|
||||||
deinter_out_count <= 0;
|
deinter_out_count <= 0;
|
||||||
end else if (enable) begin
|
end else if (enable) begin
|
||||||
if (deinterleave_out_strobe) begin
|
if (deinterleave_out_strobe) begin
|
||||||
deinter_out_count <= deinter_out_count + 2;
|
deinter_out_count <= deinter_out_count + 2;
|
||||||
end else begin
|
end //else begin
|
||||||
// wait for finishing deinterleaving current symbol
|
// wait for finishing deinterleaving current symbol
|
||||||
// only do flush for non-DATA bits, such as SIG and HT-SIG, which
|
// only do flush for non-DATA bits, such as SIG and HT-SIG, which
|
||||||
// are not scrambled
|
// are not scrambled
|
||||||
if (~do_descramble && deinter_out_count >= num_bits_to_decode) begin
|
//if (~do_descramble && deinter_out_count >= num_bits_to_decode) begin
|
||||||
flush <= 1;
|
//if (deinter_out_count >= num_bits_to_decode) begin // careful! deinter_out_count is only correct from 6M ~ 48M! under 54M, it should be 2*216, but actual value is 288!
|
||||||
end
|
//flush <= 1;
|
||||||
end
|
//end
|
||||||
if (!flush) begin
|
//end
|
||||||
|
//if (!flush) begin
|
||||||
|
if (!(deinter_out_count >= num_bits_to_decode)) begin
|
||||||
conv_in_stb <= deinterleave_out_strobe;
|
conv_in_stb <= deinterleave_out_strobe;
|
||||||
conv_in0 <= deinterleave_out[0]? 3'b111: 3'b011;
|
conv_in0 <= deinterleave_out[0]? 3'b111: 3'b011;
|
||||||
conv_in1 <= deinterleave_out[1]? 3'b111: 3'b011;
|
conv_in1 <= deinterleave_out[1]? 3'b111: 3'b011;
|
||||||
|
267
verilog/openofdm_rx.v
Normal file
267
verilog/openofdm_rx.v
Normal file
@ -0,0 +1,267 @@
|
|||||||
|
|
||||||
|
`timescale 1 ns / 1 ps
|
||||||
|
|
||||||
|
module openofdm_rx #
|
||||||
|
(
|
||||||
|
parameter integer IQ_DATA_WIDTH = 16,
|
||||||
|
parameter integer RSSI_HALF_DB_WIDTH = 11,
|
||||||
|
|
||||||
|
parameter integer C_S00_AXI_DATA_WIDTH = 32,
|
||||||
|
parameter integer C_S00_AXI_ADDR_WIDTH = 7
|
||||||
|
)
|
||||||
|
(
|
||||||
|
// intf to dot11
|
||||||
|
//input wire openofdm_core_rst,
|
||||||
|
input wire signed [(RSSI_HALF_DB_WIDTH-1):0] rssi_half_db,
|
||||||
|
input wire [(2*IQ_DATA_WIDTH-1):0] sample_in,
|
||||||
|
input wire sample_in_strobe,
|
||||||
|
|
||||||
|
output wire demod_is_ongoing, // this needs to be corrected further to indicate actual RF on going regardless the latency
|
||||||
|
// output wire pkt_ht,
|
||||||
|
output wire pkt_header_valid,
|
||||||
|
output wire pkt_header_valid_strobe,
|
||||||
|
output wire ht_unsupport,
|
||||||
|
output wire [7:0] pkt_rate,
|
||||||
|
output wire [15:0] pkt_len,
|
||||||
|
// output wire [15:0] pkt_len_total, // for interface to byte_to_word.v in rx_intf.v
|
||||||
|
output wire byte_out_strobe,
|
||||||
|
output wire [7:0] byte_out,
|
||||||
|
// output wire [15:0] byte_count_total, // for interface to byte_to_word.v in rx_intf.v
|
||||||
|
output wire [15:0] byte_count,
|
||||||
|
output wire fcs_out_strobe,
|
||||||
|
output wire fcs_ok,
|
||||||
|
|
||||||
|
// axi lite based register configuration interface
|
||||||
|
input wire s00_axi_aclk,
|
||||||
|
input wire s00_axi_aresetn,
|
||||||
|
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
|
||||||
|
input wire [2 : 0] s00_axi_awprot,
|
||||||
|
input wire s00_axi_awvalid,
|
||||||
|
output wire s00_axi_awready,
|
||||||
|
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
|
||||||
|
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
|
||||||
|
input wire s00_axi_wvalid,
|
||||||
|
output wire s00_axi_wready,
|
||||||
|
output wire [1 : 0] s00_axi_bresp,
|
||||||
|
output wire s00_axi_bvalid,
|
||||||
|
input wire s00_axi_bready,
|
||||||
|
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
|
||||||
|
input wire [2 : 0] s00_axi_arprot,
|
||||||
|
input wire s00_axi_arvalid,
|
||||||
|
output wire s00_axi_arready,
|
||||||
|
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
|
||||||
|
output wire [1 : 0] s00_axi_rresp,
|
||||||
|
output wire s00_axi_rvalid,
|
||||||
|
input wire s00_axi_rready
|
||||||
|
);
|
||||||
|
|
||||||
|
// reg0~19 for config write; from reg20 for reading status
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg0;
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg1; //
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg2;
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg3; //
|
||||||
|
/*
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg4; //
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg5; //
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg6; //
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg7; //
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg8;
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg9; //
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg10;
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg11;
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg12;
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg13;
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg14;
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg15;
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg16;
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg17;
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg18;
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg19; */
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg20; // read openofdm rx core internal state
|
||||||
|
/*
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg21;
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg22;
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg23;
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg24;
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg25;
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg26;
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg27;
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg28;
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg29;
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg30;
|
||||||
|
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg31;
|
||||||
|
*/
|
||||||
|
|
||||||
|
wire [3:0] state;
|
||||||
|
wire state_changed;
|
||||||
|
reg [31:0] state_history;
|
||||||
|
|
||||||
|
assign slv_reg20 = state_history;
|
||||||
|
|
||||||
|
always @(posedge s00_axi_aclk) begin
|
||||||
|
if (s00_axi_aresetn==0) begin
|
||||||
|
state_history <= 0;
|
||||||
|
end else if (state_changed) begin
|
||||||
|
state_history[3:0] <= state;
|
||||||
|
state_history[31:4] <= state_history[27:0];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
dot11 # (
|
||||||
|
) dot11_i (
|
||||||
|
.clock(s00_axi_aclk),
|
||||||
|
.enable( ~slv_reg1[0] ),
|
||||||
|
//.reset ( (~s00_axi_aresetn)|slv_reg0[0]|openofdm_core_rst ),
|
||||||
|
.reset ( (~s00_axi_aresetn)|slv_reg0[0] ),
|
||||||
|
|
||||||
|
.power_thres(slv_reg2[10:0]),
|
||||||
|
.min_plateau(slv_reg3),
|
||||||
|
|
||||||
|
.rssi_half_db(rssi_half_db),
|
||||||
|
|
||||||
|
.sample_in(sample_in),
|
||||||
|
.sample_in_strobe(sample_in_strobe),
|
||||||
|
|
||||||
|
// OUTPUT: bytes and FCS status
|
||||||
|
.demod_is_ongoing(demod_is_ongoing),
|
||||||
|
// .pkt_begin(),
|
||||||
|
// .pkt_ht(),
|
||||||
|
.pkt_header_valid(pkt_header_valid),
|
||||||
|
.pkt_header_valid_strobe(pkt_header_valid_strobe),
|
||||||
|
.ht_unsupport(ht_unsupport),
|
||||||
|
.pkt_rate(pkt_rate),
|
||||||
|
.pkt_len(pkt_len),
|
||||||
|
// .pkt_len_total(pkt_len_total),
|
||||||
|
.byte_out_strobe(byte_out_strobe),
|
||||||
|
.byte_out(byte_out),
|
||||||
|
// .byte_count_total(byte_count_total),
|
||||||
|
.byte_count(byte_count),
|
||||||
|
.fcs_out_strobe(fcs_out_strobe),
|
||||||
|
.fcs_ok(fcs_ok),
|
||||||
|
|
||||||
|
/////////////////////////////////////////////////////////
|
||||||
|
// DEBUG PORTS
|
||||||
|
/////////////////////////////////////////////////////////
|
||||||
|
// decode status
|
||||||
|
.state(state),
|
||||||
|
.status_code(),
|
||||||
|
.state_changed(state_changed),
|
||||||
|
|
||||||
|
// power trigger
|
||||||
|
.power_trigger(),
|
||||||
|
|
||||||
|
// sync short
|
||||||
|
.short_preamble_detected(),
|
||||||
|
.phase_offset(),
|
||||||
|
|
||||||
|
// sync long
|
||||||
|
.sync_long_metric(),
|
||||||
|
.sync_long_metric_stb(),
|
||||||
|
.long_preamble_detected(),
|
||||||
|
.sync_long_out(),
|
||||||
|
.sync_long_out_strobe(),
|
||||||
|
.sync_long_state(),
|
||||||
|
|
||||||
|
// equalizer
|
||||||
|
.equalizer_out(),
|
||||||
|
.equalizer_out_strobe(),
|
||||||
|
.equalizer_state(),
|
||||||
|
|
||||||
|
// legacy signal info
|
||||||
|
.legacy_sig_stb(),
|
||||||
|
.legacy_rate(),
|
||||||
|
.legacy_sig_rsvd(),
|
||||||
|
.legacy_len(),
|
||||||
|
.legacy_sig_parity(),
|
||||||
|
.legacy_sig_parity_ok(),
|
||||||
|
.legacy_sig_tail(),
|
||||||
|
|
||||||
|
// ht signal info
|
||||||
|
.ht_sig_stb(),
|
||||||
|
.ht_mcs(),
|
||||||
|
.ht_cbw(),
|
||||||
|
.ht_len(),
|
||||||
|
.ht_smoothing(),
|
||||||
|
.ht_not_sounding(),
|
||||||
|
.ht_aggregation(),
|
||||||
|
.ht_stbc(),
|
||||||
|
.ht_fec_coding(),
|
||||||
|
.ht_sgi(),
|
||||||
|
.ht_num_ext(),
|
||||||
|
.ht_sig_crc_ok(),
|
||||||
|
|
||||||
|
// decoding pipeline
|
||||||
|
.demod_out(),
|
||||||
|
.demod_out_strobe(),
|
||||||
|
|
||||||
|
.deinterleave_erase_out(),
|
||||||
|
.deinterleave_erase_out_strobe(),
|
||||||
|
|
||||||
|
.conv_decoder_out(),
|
||||||
|
.conv_decoder_out_stb(),
|
||||||
|
|
||||||
|
.descramble_out(),
|
||||||
|
.descramble_out_strobe()
|
||||||
|
);
|
||||||
|
|
||||||
|
openofdm_rx_s_axi # (
|
||||||
|
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
|
||||||
|
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
|
||||||
|
) openofdm_rx_s_axi_i (
|
||||||
|
.S_AXI_ACLK(s00_axi_aclk),
|
||||||
|
.S_AXI_ARESETN(s00_axi_aresetn),
|
||||||
|
.S_AXI_AWADDR(s00_axi_awaddr),
|
||||||
|
.S_AXI_AWPROT(s00_axi_awprot),
|
||||||
|
.S_AXI_AWVALID(s00_axi_awvalid),
|
||||||
|
.S_AXI_AWREADY(s00_axi_awready),
|
||||||
|
.S_AXI_WDATA(s00_axi_wdata),
|
||||||
|
.S_AXI_WSTRB(s00_axi_wstrb),
|
||||||
|
.S_AXI_WVALID(s00_axi_wvalid),
|
||||||
|
.S_AXI_WREADY(s00_axi_wready),
|
||||||
|
.S_AXI_BRESP(s00_axi_bresp),
|
||||||
|
.S_AXI_BVALID(s00_axi_bvalid),
|
||||||
|
.S_AXI_BREADY(s00_axi_bready),
|
||||||
|
.S_AXI_ARADDR(s00_axi_araddr),
|
||||||
|
.S_AXI_ARPROT(s00_axi_arprot),
|
||||||
|
.S_AXI_ARVALID(s00_axi_arvalid),
|
||||||
|
.S_AXI_ARREADY(s00_axi_arready),
|
||||||
|
.S_AXI_RDATA(s00_axi_rdata),
|
||||||
|
.S_AXI_RRESP(s00_axi_rresp),
|
||||||
|
.S_AXI_RVALID(s00_axi_rvalid),
|
||||||
|
.S_AXI_RREADY(s00_axi_rready),
|
||||||
|
|
||||||
|
.SLV_REG0(slv_reg0),
|
||||||
|
.SLV_REG1(slv_reg1),
|
||||||
|
.SLV_REG2(slv_reg2),
|
||||||
|
.SLV_REG3(slv_reg3), /*,
|
||||||
|
.SLV_REG4(slv_reg4),
|
||||||
|
.SLV_REG5(slv_reg5),
|
||||||
|
.SLV_REG6(slv_reg6),
|
||||||
|
.SLV_REG7(slv_reg7),
|
||||||
|
.SLV_REG8(slv_reg8),
|
||||||
|
.SLV_REG9(slv_reg9),
|
||||||
|
.SLV_REG10(slv_reg10),
|
||||||
|
.SLV_REG11(slv_reg11),
|
||||||
|
.SLV_REG12(slv_reg12),
|
||||||
|
.SLV_REG13(slv_reg13),
|
||||||
|
.SLV_REG14(slv_reg14),
|
||||||
|
.SLV_REG15(slv_reg15),
|
||||||
|
.SLV_REG16(slv_reg16),
|
||||||
|
.SLV_REG17(slv_reg17),
|
||||||
|
.SLV_REG18(slv_reg18),
|
||||||
|
.SLV_REG19(slv_reg19),*/
|
||||||
|
.SLV_REG20(slv_reg20)/*
|
||||||
|
.SLV_REG21(slv_reg21),
|
||||||
|
.SLV_REG22(slv_reg22),
|
||||||
|
.SLV_REG23(slv_reg23),
|
||||||
|
.SLV_REG24(slv_reg24),
|
||||||
|
.SLV_REG25(slv_reg25),
|
||||||
|
.SLV_REG26(slv_reg26),
|
||||||
|
.SLV_REG27(slv_reg27),
|
||||||
|
.SLV_REG28(slv_reg28),
|
||||||
|
.SLV_REG29(slv_reg29),
|
||||||
|
.SLV_REG30(slv_reg30),
|
||||||
|
.SLV_REG31(slv_reg31)*/
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
@ -1,7 +1,7 @@
|
|||||||
|
|
||||||
`timescale 1 ns / 1 ps
|
`timescale 1 ns / 1 ps
|
||||||
|
|
||||||
module dot11zynq_S00_AXI #
|
module openofdm_rx_s_axi #
|
||||||
(
|
(
|
||||||
// Users to add parameters here
|
// Users to add parameters here
|
||||||
|
|
||||||
@ -15,33 +15,38 @@
|
|||||||
)
|
)
|
||||||
(
|
(
|
||||||
// Users to add ports here
|
// Users to add ports here
|
||||||
input wire enable,
|
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG0,
|
||||||
input wire [31:0] sample_in,
|
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG1,
|
||||||
input wire sample_in_strobe,
|
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG2,
|
||||||
|
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG3,/*
|
||||||
output wire trigger,
|
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG4,
|
||||||
output wire ofdm_byte_valid,
|
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG5,
|
||||||
output wire [7:0] ofdm_byte,
|
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG6,
|
||||||
output wire [63:0] data_out, // only has payload, doesn't have signal
|
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG7,
|
||||||
output wire data_out_valid,
|
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG8,
|
||||||
output wire fcs_valid,
|
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG9,
|
||||||
output wire fcs_invalid,
|
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG10,
|
||||||
|
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG11,
|
||||||
output wire sig_valid,
|
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG12,
|
||||||
output wire sig_invalid,
|
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG13,
|
||||||
output reg [2:0] mcs_io,
|
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG14,
|
||||||
output wire [11:0] pkt_len_io,
|
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG15,
|
||||||
|
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG16,
|
||||||
output wire [6:0] ht_mcs_io,
|
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG17,
|
||||||
output wire [15:0] ht_pkt_len_io,
|
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG18,
|
||||||
output wire ht_sig_invalid,
|
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG19,*/
|
||||||
output wire ht_sig_valid,
|
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG20,/*
|
||||||
output reg ht_unsupported,
|
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG21,
|
||||||
|
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG22,
|
||||||
// ports to interract with fifo
|
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG23,
|
||||||
input wire fifo_empty,
|
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG24,
|
||||||
output reg rd_en,
|
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG25,
|
||||||
output wire fifo_rst,
|
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG26,
|
||||||
|
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG27,
|
||||||
|
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG28,
|
||||||
|
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG29,
|
||||||
|
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG30,
|
||||||
|
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG31,*/
|
||||||
// User ports ends
|
// User ports ends
|
||||||
// Do not modify the ports beyond this line
|
// Do not modify the ports beyond this line
|
||||||
|
|
||||||
@ -126,19 +131,6 @@
|
|||||||
// ADDR_LSB = 3 for 64 bits (n downto 3)
|
// ADDR_LSB = 3 for 64 bits (n downto 3)
|
||||||
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
|
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
|
||||||
localparam integer OPT_MEM_ADDR_BITS = 4;
|
localparam integer OPT_MEM_ADDR_BITS = 4;
|
||||||
|
|
||||||
// openofdm local parameters for ht signal condition
|
|
||||||
// erros in HT-SIGNAL
|
|
||||||
localparam E_UNSUPPORTED_MCS = 1;
|
|
||||||
localparam E_UNSUPPORTED_CBW = 2;
|
|
||||||
localparam E_HT_WRONG_RSVD = 3;
|
|
||||||
localparam E_UNSUPPORTED_STBC = 4;
|
|
||||||
localparam E_UNSUPPORTED_FEC = 5;
|
|
||||||
localparam E_UNSUPPORTED_SGI = 6;
|
|
||||||
localparam E_UNSUPPORTED_SPATIAL = 7;
|
|
||||||
localparam E_HT_WRONG_TAIL = 8;
|
|
||||||
localparam E_WRONG_CRC = 9;
|
|
||||||
|
|
||||||
//----------------------------------------------
|
//----------------------------------------------
|
||||||
//-- Signals for user logic register space example
|
//-- Signals for user logic register space example
|
||||||
//------------------------------------------------
|
//------------------------------------------------
|
||||||
@ -146,7 +138,7 @@
|
|||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
|
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
|
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
|
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
|
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;/*
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4;
|
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4;
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5;
|
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5;
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6;
|
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6;
|
||||||
@ -162,8 +154,8 @@
|
|||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16;
|
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16;
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg17;
|
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg17;
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg18;
|
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg18;
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg19;
|
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg19;*/
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg20;
|
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg20;/*
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg21;
|
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg21;
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg22;
|
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg22;
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg23;
|
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg23;
|
||||||
@ -174,12 +166,11 @@
|
|||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28;
|
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28;
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29;
|
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29;
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30;
|
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30;
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31;
|
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31;*/
|
||||||
wire slv_reg_rden;
|
wire slv_reg_rden;
|
||||||
wire slv_reg_wren;
|
wire slv_reg_wren;
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
|
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
|
||||||
integer byte_index;
|
integer byte_index;
|
||||||
reg aw_en;
|
|
||||||
|
|
||||||
// I/O Connections assignments
|
// I/O Connections assignments
|
||||||
|
|
||||||
@ -191,6 +182,27 @@
|
|||||||
assign S_AXI_RDATA = axi_rdata;
|
assign S_AXI_RDATA = axi_rdata;
|
||||||
assign S_AXI_RRESP = axi_rresp;
|
assign S_AXI_RRESP = axi_rresp;
|
||||||
assign S_AXI_RVALID = axi_rvalid;
|
assign S_AXI_RVALID = axi_rvalid;
|
||||||
|
|
||||||
|
assign SLV_REG0 = slv_reg0;
|
||||||
|
assign SLV_REG1 = slv_reg1;
|
||||||
|
assign SLV_REG2 = slv_reg2;
|
||||||
|
assign SLV_REG3 = slv_reg3;/*
|
||||||
|
assign SLV_REG4 = slv_reg4;
|
||||||
|
assign SLV_REG5 = slv_reg5;
|
||||||
|
assign SLV_REG6 = slv_reg6;
|
||||||
|
assign SLV_REG7 = slv_reg7;
|
||||||
|
assign SLV_REG8 = slv_reg8;
|
||||||
|
assign SLV_REG9 = slv_reg9;
|
||||||
|
assign SLV_REG10 = slv_reg10;
|
||||||
|
assign SLV_REG11 = slv_reg11;
|
||||||
|
assign SLV_REG12 = slv_reg12;
|
||||||
|
assign SLV_REG13 = slv_reg13;
|
||||||
|
assign SLV_REG14 = slv_reg14;
|
||||||
|
assign SLV_REG15 = slv_reg15;
|
||||||
|
assign SLV_REG16 = slv_reg16;
|
||||||
|
assign SLV_REG17 = slv_reg17;
|
||||||
|
assign SLV_REG18 = slv_reg18;
|
||||||
|
assign SLV_REG19 = slv_reg19;*/
|
||||||
// Implement axi_awready generation
|
// Implement axi_awready generation
|
||||||
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
|
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
|
||||||
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
|
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
|
||||||
@ -201,23 +213,16 @@
|
|||||||
if ( S_AXI_ARESETN == 1'b0 )
|
if ( S_AXI_ARESETN == 1'b0 )
|
||||||
begin
|
begin
|
||||||
axi_awready <= 1'b0;
|
axi_awready <= 1'b0;
|
||||||
aw_en <= 1'b1;
|
|
||||||
end
|
end
|
||||||
else
|
else
|
||||||
begin
|
begin
|
||||||
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
|
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
|
||||||
begin
|
begin
|
||||||
// slave is ready to accept write address when
|
// slave is ready to accept write address when
|
||||||
// there is a valid write address and write data
|
// there is a valid write address and write data
|
||||||
// on the write address and data bus. This design
|
// on the write address and data bus. This design
|
||||||
// expects no outstanding transactions.
|
// expects no outstanding transactions.
|
||||||
axi_awready <= 1'b1;
|
axi_awready <= 1'b1;
|
||||||
aw_en <= 1'b0;
|
|
||||||
end
|
|
||||||
else if (S_AXI_BREADY && axi_bvalid)
|
|
||||||
begin
|
|
||||||
aw_en <= 1'b1;
|
|
||||||
axi_awready <= 1'b0;
|
|
||||||
end
|
end
|
||||||
else
|
else
|
||||||
begin
|
begin
|
||||||
@ -238,7 +243,7 @@
|
|||||||
end
|
end
|
||||||
else
|
else
|
||||||
begin
|
begin
|
||||||
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
|
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
|
||||||
begin
|
begin
|
||||||
// Write Address latching
|
// Write Address latching
|
||||||
axi_awaddr <= S_AXI_AWADDR;
|
axi_awaddr <= S_AXI_AWADDR;
|
||||||
@ -259,7 +264,7 @@
|
|||||||
end
|
end
|
||||||
else
|
else
|
||||||
begin
|
begin
|
||||||
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
|
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
|
||||||
begin
|
begin
|
||||||
// slave is ready to accept write data when
|
// slave is ready to accept write data when
|
||||||
// there is a valid write address and write data
|
// there is a valid write address and write data
|
||||||
@ -287,38 +292,26 @@
|
|||||||
begin
|
begin
|
||||||
if ( S_AXI_ARESETN == 1'b0 )
|
if ( S_AXI_ARESETN == 1'b0 )
|
||||||
begin
|
begin
|
||||||
slv_reg0 <= 32'd100; // power_thresh register, 16 bit LSB used, MSB used as general reset
|
slv_reg0 <= 32'h0;
|
||||||
slv_reg1 <= 32'd80; // power window register, 16 bit LSB used
|
slv_reg1 <= 32'h0;
|
||||||
slv_reg2 <= 32'd5000000; // num sample to skip register, 32 bit used
|
slv_reg2 <= 32'h0;
|
||||||
slv_reg3 <= 32'd100; // min plateau for short synq to be detected
|
slv_reg3 <= 32'h0;/*
|
||||||
slv_reg4 <= 0;
|
slv_reg4 <= 32'h0;
|
||||||
slv_reg5 <= 0;
|
slv_reg5 <= 32'h0;
|
||||||
slv_reg6 <= 0;
|
slv_reg6 <= 32'h0;
|
||||||
slv_reg7 <= 0;
|
slv_reg7 <= 32'h0;
|
||||||
slv_reg8 <= 0;
|
slv_reg8 <= 32'h0;
|
||||||
slv_reg9 <= 0;
|
slv_reg9 <= 32'h0;
|
||||||
slv_reg10 <= 0;
|
slv_reg10 <= 32'h0;
|
||||||
slv_reg11 <= 0;
|
slv_reg11 <= 32'h0;
|
||||||
slv_reg12 <= 0;
|
slv_reg12 <= 32'h0;
|
||||||
slv_reg13 <= 0;
|
slv_reg13 <= 32'h0;
|
||||||
slv_reg14 <= 0;
|
slv_reg14 <= 32'h0;
|
||||||
slv_reg15 <= 0;
|
slv_reg15 <= 32'h0;
|
||||||
// slv_reg16 <= 0;
|
slv_reg16 <= 32'h0;
|
||||||
// slv_reg17 <= 0;
|
slv_reg17 <= 32'h0;
|
||||||
// slv_reg18 <= 0;
|
slv_reg18 <= 32'h0;
|
||||||
// slv_reg19 <= 0;
|
slv_reg19 <= 32'h0;*/
|
||||||
// slv_reg20 <= 0;
|
|
||||||
slv_reg21 <= 0;
|
|
||||||
slv_reg22 <= 0;
|
|
||||||
slv_reg23 <= 0;
|
|
||||||
slv_reg24 <= 0;
|
|
||||||
slv_reg25 <= 0;
|
|
||||||
slv_reg26 <= 0;
|
|
||||||
slv_reg27 <= 0;
|
|
||||||
slv_reg28 <= 0;
|
|
||||||
slv_reg29 <= 0;
|
|
||||||
slv_reg30 <= 0;
|
|
||||||
slv_reg31 <= 0;
|
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
if (slv_reg_wren)
|
if (slv_reg_wren)
|
||||||
@ -351,7 +344,7 @@
|
|||||||
// Respective byte enables are asserted as per write strobes
|
// Respective byte enables are asserted as per write strobes
|
||||||
// Slave register 3
|
// Slave register 3
|
||||||
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||||
end
|
end /*
|
||||||
5'h04:
|
5'h04:
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||||
@ -436,123 +429,123 @@
|
|||||||
// Slave register 15
|
// Slave register 15
|
||||||
slv_reg15[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
slv_reg15[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||||
end
|
end
|
||||||
// 5'h10:
|
5'h10:
|
||||||
// for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||||
// if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||||
// // Respective byte enables are asserted as per write strobes
|
// Respective byte enables are asserted as per write strobes
|
||||||
// // Slave register 16
|
// Slave register 16
|
||||||
// slv_reg16[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
slv_reg16[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||||
// end
|
end
|
||||||
// 5'h11:
|
5'h11:
|
||||||
// for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||||
// if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||||
// // Respective byte enables are asserted as per write strobes
|
// Respective byte enables are asserted as per write strobes
|
||||||
// // Slave register 17
|
// Slave register 17
|
||||||
// slv_reg17[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
slv_reg17[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||||
// end
|
end
|
||||||
// 5'h12:
|
5'h12:
|
||||||
// for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||||
// if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||||
// // Respective byte enables are asserted as per write strobes
|
// Respective byte enables are asserted as per write strobes
|
||||||
// // Slave register 18
|
// Slave register 18
|
||||||
// slv_reg18[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
slv_reg18[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||||
// end
|
end
|
||||||
// 5'h13:
|
5'h13:
|
||||||
// for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||||
// if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||||
// // Respective byte enables are asserted as per write strobes
|
// Respective byte enables are asserted as per write strobes
|
||||||
// // Slave register 19
|
// Slave register 19
|
||||||
// slv_reg19[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
slv_reg19[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||||
// end
|
end
|
||||||
// 5'h14:
|
5'h14:
|
||||||
// for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||||
// if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||||
// // Respective byte enables are asserted as per write strobes
|
// Respective byte enables are asserted as per write strobes
|
||||||
// // Slave register 20
|
// Slave register 20
|
||||||
//slv_reg20[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
//slv_reg20[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||||
// end
|
end
|
||||||
5'h15:
|
5'h15:
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||||
// Respective byte enables are asserted as per write strobes
|
// Respective byte enables are asserted as per write strobes
|
||||||
// Slave register 21
|
// Slave register 21
|
||||||
slv_reg21[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
//slv_reg21[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||||
end
|
end
|
||||||
5'h16:
|
5'h16:
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||||
// Respective byte enables are asserted as per write strobes
|
// Respective byte enables are asserted as per write strobes
|
||||||
// Slave register 22
|
// Slave register 22
|
||||||
slv_reg22[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
//slv_reg22[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||||
end
|
end
|
||||||
5'h17:
|
5'h17:
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||||
// Respective byte enables are asserted as per write strobes
|
// Respective byte enables are asserted as per write strobes
|
||||||
// Slave register 23
|
// Slave register 23
|
||||||
slv_reg23[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
//slv_reg23[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||||
end
|
end
|
||||||
5'h18:
|
5'h18:
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||||
// Respective byte enables are asserted as per write strobes
|
// Respective byte enables are asserted as per write strobes
|
||||||
// Slave register 24
|
// Slave register 24
|
||||||
slv_reg24[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
//slv_reg24[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||||
end
|
end
|
||||||
5'h19:
|
5'h19:
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||||
// Respective byte enables are asserted as per write strobes
|
// Respective byte enables are asserted as per write strobes
|
||||||
// Slave register 25
|
// Slave register 25
|
||||||
slv_reg25[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
//slv_reg25[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||||
end
|
end
|
||||||
5'h1A:
|
5'h1A:
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||||
// Respective byte enables are asserted as per write strobes
|
// Respective byte enables are asserted as per write strobes
|
||||||
// Slave register 26
|
// Slave register 26
|
||||||
slv_reg26[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
//slv_reg26[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||||
end
|
end
|
||||||
5'h1B:
|
5'h1B:
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||||
// Respective byte enables are asserted as per write strobes
|
// Respective byte enables are asserted as per write strobes
|
||||||
// Slave register 27
|
// Slave register 27
|
||||||
slv_reg27[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
//slv_reg27[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||||
end
|
end
|
||||||
5'h1C:
|
5'h1C:
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||||
// Respective byte enables are asserted as per write strobes
|
// Respective byte enables are asserted as per write strobes
|
||||||
// Slave register 28
|
// Slave register 28
|
||||||
slv_reg28[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
//slv_reg28[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||||
end
|
end
|
||||||
5'h1D:
|
5'h1D:
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||||
// Respective byte enables are asserted as per write strobes
|
// Respective byte enables are asserted as per write strobes
|
||||||
// Slave register 29
|
// Slave register 29
|
||||||
slv_reg29[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
//slv_reg29[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||||
end
|
end
|
||||||
5'h1E:
|
5'h1E:
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||||
// Respective byte enables are asserted as per write strobes
|
// Respective byte enables are asserted as per write strobes
|
||||||
// Slave register 30
|
// Slave register 30
|
||||||
slv_reg30[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
//slv_reg30[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||||
end
|
end
|
||||||
5'h1F:
|
5'h1F:
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||||
// Respective byte enables are asserted as per write strobes
|
// Respective byte enables are asserted as per write strobes
|
||||||
// Slave register 31
|
// Slave register 31
|
||||||
slv_reg31[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
//slv_reg31[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||||
end
|
end */
|
||||||
default : begin
|
default : begin
|
||||||
slv_reg0 <= slv_reg0;
|
slv_reg0 <= slv_reg0;
|
||||||
slv_reg1 <= slv_reg1;
|
slv_reg1 <= slv_reg1;
|
||||||
slv_reg2 <= slv_reg2;
|
slv_reg2 <= slv_reg2;
|
||||||
slv_reg3 <= slv_reg3;
|
slv_reg3 <= slv_reg3;/*
|
||||||
slv_reg4 <= slv_reg4;
|
slv_reg4 <= slv_reg4;
|
||||||
slv_reg5 <= slv_reg5;
|
slv_reg5 <= slv_reg5;
|
||||||
slv_reg6 <= slv_reg6;
|
slv_reg6 <= slv_reg6;
|
||||||
@ -565,22 +558,22 @@
|
|||||||
slv_reg13 <= slv_reg13;
|
slv_reg13 <= slv_reg13;
|
||||||
slv_reg14 <= slv_reg14;
|
slv_reg14 <= slv_reg14;
|
||||||
slv_reg15 <= slv_reg15;
|
slv_reg15 <= slv_reg15;
|
||||||
// slv_reg16 <= slv_reg16;
|
slv_reg16 <= slv_reg16;
|
||||||
// slv_reg17 <= slv_reg17;
|
slv_reg17 <= slv_reg17;
|
||||||
// slv_reg18 <= slv_reg18;
|
slv_reg18 <= slv_reg18;
|
||||||
// slv_reg19 <= slv_reg19;
|
slv_reg19 <= slv_reg19;*/
|
||||||
//slv_reg20 <= slv_reg20;
|
//slv_reg20 <= slv_reg20;
|
||||||
slv_reg21 <= slv_reg21;
|
//slv_reg21 <= slv_reg21;
|
||||||
slv_reg22 <= slv_reg22;
|
//slv_reg22 <= slv_reg22;
|
||||||
slv_reg23 <= slv_reg23;
|
//slv_reg23 <= slv_reg23;
|
||||||
slv_reg24 <= slv_reg24;
|
//slv_reg24 <= slv_reg24;
|
||||||
slv_reg25 <= slv_reg25;
|
//slv_reg25 <= slv_reg25;
|
||||||
slv_reg26 <= slv_reg26;
|
//slv_reg26 <= slv_reg26;
|
||||||
slv_reg27 <= slv_reg27;
|
//slv_reg27 <= slv_reg27;
|
||||||
slv_reg28 <= slv_reg28;
|
//slv_reg28 <= slv_reg28;
|
||||||
slv_reg29 <= slv_reg29;
|
//slv_reg29 <= slv_reg29;
|
||||||
slv_reg30 <= slv_reg30;
|
//slv_reg30 <= slv_reg30;
|
||||||
slv_reg31 <= slv_reg31;
|
//slv_reg31 <= slv_reg31;
|
||||||
end
|
end
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
@ -692,7 +685,7 @@
|
|||||||
5'h00 : reg_data_out <= slv_reg0;
|
5'h00 : reg_data_out <= slv_reg0;
|
||||||
5'h01 : reg_data_out <= slv_reg1;
|
5'h01 : reg_data_out <= slv_reg1;
|
||||||
5'h02 : reg_data_out <= slv_reg2;
|
5'h02 : reg_data_out <= slv_reg2;
|
||||||
5'h03 : reg_data_out <= slv_reg3;
|
5'h03 : reg_data_out <= slv_reg3;/*
|
||||||
5'h04 : reg_data_out <= slv_reg4;
|
5'h04 : reg_data_out <= slv_reg4;
|
||||||
5'h05 : reg_data_out <= slv_reg5;
|
5'h05 : reg_data_out <= slv_reg5;
|
||||||
5'h06 : reg_data_out <= slv_reg6;
|
5'h06 : reg_data_out <= slv_reg6;
|
||||||
@ -708,8 +701,8 @@
|
|||||||
5'h10 : reg_data_out <= slv_reg16;
|
5'h10 : reg_data_out <= slv_reg16;
|
||||||
5'h11 : reg_data_out <= slv_reg17;
|
5'h11 : reg_data_out <= slv_reg17;
|
||||||
5'h12 : reg_data_out <= slv_reg18;
|
5'h12 : reg_data_out <= slv_reg18;
|
||||||
5'h13 : reg_data_out <= slv_reg19;
|
5'h13 : reg_data_out <= slv_reg19;*/
|
||||||
5'h14 : reg_data_out <= slv_reg20;
|
5'h14 : reg_data_out <= slv_reg20;/*
|
||||||
5'h15 : reg_data_out <= slv_reg21;
|
5'h15 : reg_data_out <= slv_reg21;
|
||||||
5'h16 : reg_data_out <= slv_reg22;
|
5'h16 : reg_data_out <= slv_reg22;
|
||||||
5'h17 : reg_data_out <= slv_reg23;
|
5'h17 : reg_data_out <= slv_reg23;
|
||||||
@ -720,7 +713,7 @@
|
|||||||
5'h1C : reg_data_out <= slv_reg28;
|
5'h1C : reg_data_out <= slv_reg28;
|
||||||
5'h1D : reg_data_out <= slv_reg29;
|
5'h1D : reg_data_out <= slv_reg29;
|
||||||
5'h1E : reg_data_out <= slv_reg30;
|
5'h1E : reg_data_out <= slv_reg30;
|
||||||
5'h1F : reg_data_out <= slv_reg31;
|
5'h1F : reg_data_out <= slv_reg31;*/
|
||||||
default : reg_data_out <= 0;
|
default : reg_data_out <= 0;
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
@ -745,209 +738,40 @@
|
|||||||
end
|
end
|
||||||
|
|
||||||
// Add user logic here
|
// Add user logic here
|
||||||
(* mark_debug = "true" *) reg num_sample_changed;
|
|
||||||
(* mark_debug = "true" *) wire [31:0] num_sample_delayed ;
|
|
||||||
(* mark_debug = "true" *) wire reset = ~S_AXI_ARESETN | slv_reg0[C_S_AXI_DATA_WIDTH-1];
|
|
||||||
assign fifo_rst = reset ;
|
|
||||||
delayT #(.DATA_WIDTH(32), .DELAY(1)) num_sp_to_skip_delay_inst (
|
|
||||||
.clock(S_AXI_ACLK),
|
|
||||||
.reset(reset),
|
|
||||||
.data_in(slv_reg2),
|
|
||||||
.data_out(num_sample_delayed)
|
|
||||||
);
|
|
||||||
|
|
||||||
// write process for status registers to read header information
|
|
||||||
always @( posedge S_AXI_ACLK )
|
|
||||||
begin
|
|
||||||
if( reset ) begin
|
|
||||||
slv_reg16 <= 0;
|
|
||||||
slv_reg17 <= 0;
|
|
||||||
slv_reg18 <= 0;
|
|
||||||
slv_reg19 <= 0;
|
|
||||||
slv_reg20 <= 0;
|
|
||||||
end else begin
|
|
||||||
if (sig_valid) begin
|
|
||||||
slv_reg16 <= {29'b0, mcs_io} ;
|
|
||||||
slv_reg17 <= {20'b0, legacy_len} ;
|
|
||||||
end
|
|
||||||
if (ht_sig_valid) begin
|
|
||||||
slv_reg18 <= {25'b0, ht_mcs_io} ;
|
|
||||||
slv_reg19 <= {16'b0, ht_pkt_len_io} ;
|
|
||||||
end
|
|
||||||
if (fcs_valid)
|
|
||||||
slv_reg20 <= slv_reg20 + 1 ;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
always @( posedge S_AXI_ACLK )
|
always @( posedge S_AXI_ACLK )
|
||||||
begin
|
begin
|
||||||
if ( S_AXI_ARESETN == 1'b0 )
|
if ( S_AXI_ARESETN == 1'b0 )
|
||||||
num_sample_changed <= 1'b0 ;
|
|
||||||
else
|
|
||||||
begin
|
begin
|
||||||
if( num_sample_delayed == slv_reg2)
|
slv_reg20 <= 32'h0;/*
|
||||||
num_sample_changed <= 1'b0 ;
|
slv_reg21 <= 32'h0;
|
||||||
else
|
slv_reg22 <= 32'h0;
|
||||||
num_sample_changed <= 1'b1 ;
|
slv_reg23 <= 32'h0;
|
||||||
|
slv_reg24 <= 32'h0;
|
||||||
end
|
slv_reg25 <= 32'h0;
|
||||||
end
|
slv_reg26 <= 32'h0;
|
||||||
(* mark_debug = "true" *) wire [31:0] phase_offset ;
|
slv_reg27 <= 32'h0;
|
||||||
(* mark_debug = "true" *) wire short_preamble_detected ;
|
slv_reg28 <= 32'h0;
|
||||||
(* mark_debug = "true" *) wire [3:0] state;
|
slv_reg29 <= 32'h0;
|
||||||
(* mark_debug = "true" *) wire [3:0] status_code;
|
slv_reg30 <= 32'h0;
|
||||||
(* mark_debug = "true" *) wire state_changed;
|
slv_reg31 <= 32'h0;*/
|
||||||
|
|
||||||
(* mark_debug = "true" *) wire [31:0] sync_long_metric;
|
|
||||||
(* mark_debug = "true" *) wire sync_long_metric_stb;
|
|
||||||
(* mark_debug = "true" *) wire long_preamble_detected;
|
|
||||||
(* mark_debug = "true" *) wire [31:0] sync_long_out;
|
|
||||||
(* mark_debug = "true" *) wire sync_long_out_strobe;
|
|
||||||
(* mark_debug = "true" *) wire [2:0] sync_long_state;
|
|
||||||
|
|
||||||
(* mark_debug = "true" *) wire pkt_begin;
|
|
||||||
(* mark_debug = "true" *) wire pkt_ht ;
|
|
||||||
(* mark_debug = "true" *) wire [7:0] pkt_rate ;
|
|
||||||
(* mark_debug = "true" *) wire [15:0] pkt_len ;
|
|
||||||
(* mark_debug = "true" *) wire [7:0] byte_out ;
|
|
||||||
(* mark_debug = "true" *) wire fcs_out_strobe;
|
|
||||||
(* mark_debug = "true" *) wire fcs_ok ;
|
|
||||||
(* mark_debug = "true" *) wire byte_out_strobe;
|
|
||||||
|
|
||||||
(* mark_debug = "true" *) reg [3:0] rd_en_counter ;
|
|
||||||
|
|
||||||
wire [3:0] legacy_rate;
|
|
||||||
wire [11:0] legacy_len;
|
|
||||||
wire legacy_sig_parity_ok;
|
|
||||||
wire legacy_sig_stb;
|
|
||||||
wire [2:0] mcs_sel = legacy_rate[2:0] ;
|
|
||||||
|
|
||||||
wire ht_sig_stb;
|
|
||||||
wire ht_sig_crc_ok;
|
|
||||||
|
|
||||||
// assign top level output to spy signal
|
|
||||||
assign ofdm_byte = byte_out ;
|
|
||||||
assign ofdm_byte_valid = byte_out_strobe ;
|
|
||||||
assign fcs_valid = fcs_ok & fcs_out_strobe ;
|
|
||||||
assign fcs_invalid = (~fcs_ok) & fcs_out_strobe;
|
|
||||||
assign pkt_len_io = legacy_len ;
|
|
||||||
assign sig_valid = legacy_sig_stb & legacy_sig_parity_ok;
|
|
||||||
assign sig_invalid = (~legacy_sig_parity_ok) & legacy_sig_stb;
|
|
||||||
|
|
||||||
always @ (mcs_sel)
|
|
||||||
case (mcs_sel)
|
|
||||||
3'b000: mcs_io = 6;
|
|
||||||
3'b001: mcs_io = 4;
|
|
||||||
3'b010: mcs_io = 2;
|
|
||||||
3'b011: mcs_io = 0;
|
|
||||||
3'b100: mcs_io = 7;
|
|
||||||
3'b101: mcs_io = 5;
|
|
||||||
3'b110: mcs_io = 3;
|
|
||||||
3'b111: mcs_io = 1;
|
|
||||||
default: mcs_io = 0;
|
|
||||||
endcase
|
|
||||||
|
|
||||||
assign ht_sig_valid = ht_sig_stb & ht_sig_crc_ok ;
|
|
||||||
assign ht_sig_invalid = ht_sig_stb & (~ht_sig_crc_ok) ;
|
|
||||||
|
|
||||||
always @ (state or status_code)
|
|
||||||
begin
|
|
||||||
|
|
||||||
if(state == 13) // ht sig error state
|
|
||||||
ht_unsupported = (status_code == E_UNSUPPORTED_MCS) || (status_code == E_UNSUPPORTED_CBW) || (status_code == E_UNSUPPORTED_STBC) || (status_code == E_UNSUPPORTED_FEC) || (status_code == E_UNSUPPORTED_SGI) || (status_code == E_UNSUPPORTED_SPATIAL);
|
|
||||||
else
|
|
||||||
ht_unsupported = 0;
|
|
||||||
|
|
||||||
end
|
|
||||||
|
|
||||||
//
|
|
||||||
|
|
||||||
always @( posedge S_AXI_ACLK )
|
|
||||||
begin
|
|
||||||
if( reset == 1'b1 )
|
|
||||||
begin
|
|
||||||
rd_en_counter <= 4'b0 ;
|
|
||||||
rd_en <= 1'b0 ;
|
|
||||||
end
|
end
|
||||||
else
|
else
|
||||||
begin
|
begin
|
||||||
if( enable == 1'b1 )
|
slv_reg20 <= SLV_REG20;/*
|
||||||
begin
|
slv_reg21 <= SLV_REG21;
|
||||||
rd_en_counter = rd_en_counter + 1 ;
|
slv_reg22 <= SLV_REG22;
|
||||||
if(rd_en_counter == 4'd5)
|
slv_reg23 <= SLV_REG23;
|
||||||
begin
|
slv_reg24 <= SLV_REG24;
|
||||||
rd_en_counter = 4'b0 ;
|
slv_reg25 <= SLV_REG25;
|
||||||
if (~fifo_empty)
|
slv_reg26 <= SLV_REG26;
|
||||||
rd_en <= 1'b1;
|
slv_reg27 <= SLV_REG27;
|
||||||
else
|
slv_reg28 <= SLV_REG28;
|
||||||
rd_en <= 1'b0 ;
|
slv_reg29 <= SLV_REG29;
|
||||||
|
slv_reg30 <= SLV_REG30;
|
||||||
end
|
slv_reg31 <= SLV_REG31;*/
|
||||||
else
|
|
||||||
rd_en <= 1'b0 ;
|
|
||||||
end
|
|
||||||
|
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
||||||
dot11 dot11_inst (
|
|
||||||
.clock(S_AXI_ACLK),
|
|
||||||
.enable(enable),
|
|
||||||
.reset(reset),
|
|
||||||
|
|
||||||
.sample_in(sample_in),
|
|
||||||
.sample_in_strobe(sample_in_strobe),
|
|
||||||
|
|
||||||
.power_thres(slv_reg0[15:0]),
|
|
||||||
.window_size(slv_reg1[15:0]),
|
|
||||||
.num_sample_to_skip(slv_reg2),
|
|
||||||
.num_sample_changed(num_sample_changed),
|
|
||||||
.min_plateau(slv_reg3),
|
|
||||||
// OUTPUT: bytes and FCS status
|
|
||||||
.pkt_begin(pkt_begin),
|
|
||||||
.pkt_ht(pkt_ht),
|
|
||||||
.pkt_rate(pkt_rate),
|
|
||||||
.pkt_len(pkt_len),
|
|
||||||
.byte_out_strobe(byte_out_strobe),
|
|
||||||
.byte_out(byte_out),
|
|
||||||
.data_out(data_out),
|
|
||||||
.data_out_valid(data_out_valid),
|
|
||||||
.fcs_out_strobe(fcs_out_strobe),
|
|
||||||
.fcs_ok(fcs_ok),
|
|
||||||
|
|
||||||
// debug info
|
|
||||||
.state(state),
|
|
||||||
.status_code(status_code),
|
|
||||||
.state_changed(state_changed),
|
|
||||||
.power_trigger(trigger),
|
|
||||||
.short_preamble_detected(short_preamble_detected),
|
|
||||||
.phase_offset(phase_offset),
|
|
||||||
|
|
||||||
.sync_long_metric(sync_long_metric),
|
|
||||||
.sync_long_metric_stb(sync_long_metric_stb),
|
|
||||||
.long_preamble_detected(long_preamble_detected),
|
|
||||||
.sync_long_out(sync_long_out),
|
|
||||||
.sync_long_out_strobe(sync_long_out_strobe),
|
|
||||||
.sync_long_state(sync_long_state),
|
|
||||||
|
|
||||||
.legacy_rate(legacy_rate),
|
|
||||||
//.legacy_sig_rsvd(legacy_sig_rsvd),
|
|
||||||
.legacy_len(legacy_len),
|
|
||||||
//.legacy_sig_parity(legacy_sig_parity),
|
|
||||||
.legacy_sig_parity_ok(legacy_sig_parity_ok),
|
|
||||||
//.legacy_sig_tail(legacy_sig_tail),
|
|
||||||
.legacy_sig_stb(legacy_sig_stb),
|
|
||||||
//.sig_bits_spy(sig_bits_spy),
|
|
||||||
//.byte_count_spy(byte_count_spy),
|
|
||||||
|
|
||||||
.ht_sig_stb(ht_sig_stb),
|
|
||||||
.ht_mcs(ht_mcs_io),
|
|
||||||
.ht_len(ht_pkt_len_io),
|
|
||||||
.ht_sig_crc_ok(ht_sig_crc_ok)
|
|
||||||
|
|
||||||
|
|
||||||
);
|
|
||||||
// User logic ends
|
// User logic ends
|
||||||
|
|
||||||
endmodule
|
endmodule
|
@ -4,14 +4,13 @@ module power_trigger
|
|||||||
input enable,
|
input enable,
|
||||||
input reset,
|
input reset,
|
||||||
|
|
||||||
|
input set_stb,
|
||||||
|
input [7:0] set_addr,
|
||||||
|
input [31:0] set_data,
|
||||||
|
|
||||||
input [31:0] sample_in,
|
input [31:0] sample_in,
|
||||||
input sample_in_strobe,
|
input sample_in_strobe,
|
||||||
input [15:0] power_thres,
|
|
||||||
input [15:0] window_size,
|
|
||||||
input [31:0] num_sample_to_skip,
|
|
||||||
input num_sample_changed,
|
|
||||||
|
|
||||||
output [1:0] pw_state_spy,
|
|
||||||
output reg trigger
|
output reg trigger
|
||||||
);
|
);
|
||||||
`include "common_params.v"
|
`include "common_params.v"
|
||||||
@ -19,20 +18,34 @@ module power_trigger
|
|||||||
localparam S_SKIP = 0;
|
localparam S_SKIP = 0;
|
||||||
localparam S_IDLE = 1;
|
localparam S_IDLE = 1;
|
||||||
localparam S_PACKET = 2;
|
localparam S_PACKET = 2;
|
||||||
(* mark_debug = "true" *) reg [1:0] state;
|
reg [1:0] state;
|
||||||
|
|
||||||
|
wire [15:0] power_thres;
|
||||||
|
wire [15:0] window_size;
|
||||||
|
wire [31:0] num_sample_to_skip;
|
||||||
|
wire num_sample_changed;
|
||||||
|
|
||||||
(* mark_debug = "true" *) wire [15:0] power_thres;
|
|
||||||
(* mark_debug = "true" *) wire [15:0] window_size;
|
|
||||||
(* mark_debug = "true" *) wire [31:0] num_sample_to_skip;
|
|
||||||
(* mark_debug = "true" *) wire num_sample_changed;
|
|
||||||
(* mark_debug = "true" *) wire sample_in_strobe_dbg;
|
|
||||||
assign sample_in_strobe_dbg = sample_in_strobe ;
|
|
||||||
|
|
||||||
reg [31:0] sample_count;
|
reg [31:0] sample_count;
|
||||||
|
|
||||||
(* mark_debug = "true" *) wire [15:0] input_i = sample_in[31:16];
|
wire [15:0] input_i = sample_in[31:16];
|
||||||
reg [15:0] abs_i;
|
reg [15:0] abs_i;
|
||||||
assign pw_state_spy = state ;
|
|
||||||
|
// threshold to claim a power trigger.
|
||||||
|
setting_reg #(.my_addr(SR_POWER_THRES), .width(16), .at_reset(100)) sr_0 (
|
||||||
|
.clk(clock), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
|
||||||
|
.out(power_thres), .changed());
|
||||||
|
|
||||||
|
// power trigger window
|
||||||
|
setting_reg #(.my_addr(SR_POWER_WINDOW), .width(16), .at_reset(80)) sr_1 (
|
||||||
|
.clk(clock), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
|
||||||
|
.out(window_size), .changed());
|
||||||
|
|
||||||
|
// num samples to skip initially
|
||||||
|
setting_reg #(.my_addr(SR_SKIP_SAMPLE), .width(32), .at_reset(5000000)) sr_2 (
|
||||||
|
.clk(clock), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
|
||||||
|
.out(num_sample_to_skip), .changed(num_sample_changed));
|
||||||
|
|
||||||
|
|
||||||
always @(posedge clock) begin
|
always @(posedge clock) begin
|
||||||
if (reset) begin
|
if (reset) begin
|
||||||
|
@ -18,7 +18,7 @@ module sync_long (
|
|||||||
output reg [31:0] sample_out,
|
output reg [31:0] sample_out,
|
||||||
output reg sample_out_strobe,
|
output reg sample_out_strobe,
|
||||||
|
|
||||||
output reg [2:0] state
|
(* mark_debug = "true" *) output reg [2:0] state
|
||||||
);
|
);
|
||||||
`include "common_params.v"
|
`include "common_params.v"
|
||||||
|
|
||||||
@ -26,13 +26,13 @@ localparam IN_BUF_LEN_SHIFT = 8;
|
|||||||
|
|
||||||
localparam NUM_STS_TAIL = 32;
|
localparam NUM_STS_TAIL = 32;
|
||||||
|
|
||||||
(* mark_debug = "true" *) reg [15:0] in_offset;
|
reg [15:0] in_offset;
|
||||||
(* mark_debug = "true" *) reg [IN_BUF_LEN_SHIFT-1:0] in_waddr;
|
reg [IN_BUF_LEN_SHIFT-1:0] in_waddr;
|
||||||
(* mark_debug = "true" *) reg [IN_BUF_LEN_SHIFT-1:0] in_raddr;
|
reg [IN_BUF_LEN_SHIFT-1:0] in_raddr;
|
||||||
(* mark_debug = "true" *) wire [IN_BUF_LEN_SHIFT-1:0] gi_skip = short_gi? 9: 17;
|
wire [IN_BUF_LEN_SHIFT-1:0] gi_skip = short_gi? 9: 17;
|
||||||
(* mark_debug = "true" *) reg signed [31:0] num_input_produced;
|
reg signed [31:0] num_input_produced;
|
||||||
(* mark_debug = "true" *) reg signed [31:0] num_input_consumed;
|
reg signed [31:0] num_input_consumed;
|
||||||
(* mark_debug = "true" *) reg signed [31:0] num_input_avail;
|
reg signed [31:0] num_input_avail;
|
||||||
|
|
||||||
reg [2:0] mult_stage;
|
reg [2:0] mult_stage;
|
||||||
reg [1:0] sum_stage;
|
reg [1:0] sum_stage;
|
||||||
@ -51,7 +51,7 @@ reg signed [31:0] phase_correction;
|
|||||||
reg signed [31:0] next_phase_correction;
|
reg signed [31:0] next_phase_correction;
|
||||||
|
|
||||||
reg reset_delay ; // add reset signal for fft, somehow all kinds of event flag raises when feeding real rf signal, maybe reset will help
|
reg reset_delay ; // add reset signal for fft, somehow all kinds of event flag raises when feeding real rf signal, maybe reset will help
|
||||||
(* mark_debug = "true" *) wire fft_resetn ;
|
wire fft_resetn ;
|
||||||
|
|
||||||
always @(posedge clock) begin
|
always @(posedge clock) begin
|
||||||
reset_delay = reset ;
|
reset_delay = reset ;
|
||||||
@ -75,7 +75,7 @@ reg [31:0] metric_max1;
|
|||||||
reg [(IN_BUF_LEN_SHIFT-1):0] addr1;
|
reg [(IN_BUF_LEN_SHIFT-1):0] addr1;
|
||||||
reg [31:0] metric_max2;
|
reg [31:0] metric_max2;
|
||||||
reg [(IN_BUF_LEN_SHIFT-1):0] addr2;
|
reg [(IN_BUF_LEN_SHIFT-1):0] addr2;
|
||||||
(* mark_debug = "true" *) reg [15:0] gap;
|
reg [15:0] gap;
|
||||||
|
|
||||||
reg [31:0] cross_corr_buf[0:15];
|
reg [31:0] cross_corr_buf[0:15];
|
||||||
|
|
||||||
@ -124,27 +124,37 @@ localparam S_WAIT_FOR_SECOND_PEAK = 2;
|
|||||||
localparam S_IDLE = 3;
|
localparam S_IDLE = 3;
|
||||||
localparam S_FFT = 4;
|
localparam S_FFT = 4;
|
||||||
|
|
||||||
(* mark_debug = "true" *) reg fft_start;
|
reg fft_start;
|
||||||
(* mark_debug = "true" *) wire fft_in_stb;
|
//wire fft_start_delayed;
|
||||||
(* mark_debug = "true" *) reg fft_loading;
|
|
||||||
(* mark_debug = "true" *) wire signed [15:0] fft_in_re;
|
(* mark_debug = "false" *) wire fft_in_stb;
|
||||||
(* mark_debug = "true" *) wire signed [15:0] fft_in_im;
|
(* mark_debug = "false" *) reg fft_loading;
|
||||||
(* mark_debug = "true" *) wire [22:0] fft_out_re;
|
(* mark_debug = "false" *) wire signed [15:0] fft_in_re;
|
||||||
(* mark_debug = "true" *) wire [22:0] fft_out_im;
|
(* mark_debug = "false" *) wire signed [15:0] fft_in_im;
|
||||||
(* mark_debug = "true" *) wire fft_ready;
|
(* mark_debug = "false" *) wire [22:0] fft_out_re;
|
||||||
(* mark_debug = "true" *) wire fft_done;
|
(* mark_debug = "false" *) wire [22:0] fft_out_im;
|
||||||
(* mark_debug = "true" *) wire fft_busy;
|
(* mark_debug = "false" *) wire fft_ready;
|
||||||
(* mark_debug = "true" *) wire fft_valid;
|
(* mark_debug = "false" *) wire fft_done;
|
||||||
|
(* mark_debug = "false" *) wire fft_busy;
|
||||||
|
(* mark_debug = "false" *) wire fft_valid;
|
||||||
|
|
||||||
wire [31:0] fft_out = {fft_out_re[22:7], fft_out_im[22:7]};
|
wire [31:0] fft_out = {fft_out_re[22:7], fft_out_im[22:7]};
|
||||||
|
|
||||||
(* mark_debug = "true" *) wire signed [15:0] raw_i;
|
wire signed [15:0] raw_i;
|
||||||
(* mark_debug = "true" *) wire signed [15:0] raw_q;
|
wire signed [15:0] raw_q;
|
||||||
(* mark_debug = "true" *) reg raw_stb;
|
reg raw_stb;
|
||||||
wire idle_line1, idle_line2 ;
|
wire idle_line1, idle_line2 ;
|
||||||
(* mark_debug = "true" *) wire fft_din_data_tlast_delayed ;
|
reg fft_din_data_tlast ;
|
||||||
(* mark_debug = "true" *) reg fft_din_data_tlast ;
|
(* mark_debug = "false" *) wire fft_din_data_tlast_delayed ;
|
||||||
(* mark_debug = "true" *) wire m_axis_data_tlast, s_axis_config_tready, event_frame_started, event_tlast_unexpected, event_tlast_missing, event_status_channel_halt, event_data_in_channel_halt, event_data_out_channel_halt;
|
(* mark_debug = "false" *) wire event_frame_started;
|
||||||
|
(* mark_debug = "false" *) wire event_tlast_unexpected;
|
||||||
|
(* mark_debug = "false" *) wire event_tlast_missing;
|
||||||
|
(* mark_debug = "false" *) wire event_status_channel_halt;
|
||||||
|
(* mark_debug = "false" *) wire event_data_in_channel_halt;
|
||||||
|
(* mark_debug = "false" *) wire event_data_out_channel_halt;
|
||||||
|
(* mark_debug = "false" *) wire s_axis_config_tready;
|
||||||
|
(* mark_debug = "false" *) wire m_axis_data_tlast;
|
||||||
|
|
||||||
ram_2port #(.DWIDTH(32), .AWIDTH(IN_BUF_LEN_SHIFT)) in_buf (
|
ram_2port #(.DWIDTH(32), .AWIDTH(IN_BUF_LEN_SHIFT)) in_buf (
|
||||||
.clka(clock),
|
.clka(clock),
|
||||||
.ena(1),
|
.ena(1),
|
||||||
@ -186,9 +196,26 @@ delayT #(.DATA_WIDTH(1), .DELAY(10)) fft_delay_inst (
|
|||||||
.data_out(fft_din_data_tlast_delayed)
|
.data_out(fft_din_data_tlast_delayed)
|
||||||
);
|
);
|
||||||
|
|
||||||
|
///the fft7_1 isntance is commented out, as it is upgraded to fft9 version
|
||||||
|
/*xfft_v7_1 dft_inst (
|
||||||
|
.clk(clock),
|
||||||
|
.fwd_inv(1),
|
||||||
|
.start(fft_start_delayed),
|
||||||
|
.fwd_inv_we(1),
|
||||||
|
|
||||||
|
.xn_re(fft_in_re),
|
||||||
|
.xn_im(fft_in_im),
|
||||||
|
.xk_re(fft_out_re),
|
||||||
|
.xk_im(fft_out_im),
|
||||||
|
.rfd(fft_ready),
|
||||||
|
.done(fft_done),
|
||||||
|
.busy(fft_busy),
|
||||||
|
.dv(fft_valid)
|
||||||
|
);*/
|
||||||
|
|
||||||
|
|
||||||
xfft_v9 dft_inst (
|
xfft_v9 dft_inst (
|
||||||
.aclk(clock),
|
.aclk(clock), // input wire aclk
|
||||||
.aresetn(fft_resetn),
|
.aresetn(fft_resetn),
|
||||||
.s_axis_config_tdata({7'b0, 1'b1}), // input wire [7 : 0] s_axis_config_tdata, use LSB to indicate it is forward transform, the rest should be ignored
|
.s_axis_config_tdata({7'b0, 1'b1}), // input wire [7 : 0] s_axis_config_tdata, use LSB to indicate it is forward transform, the rest should be ignored
|
||||||
.s_axis_config_tvalid(1'b1), // input wire s_axis_config_tvalid
|
.s_axis_config_tvalid(1'b1), // input wire s_axis_config_tvalid
|
||||||
|
@ -31,7 +31,7 @@ wire mag_sq_stb;
|
|||||||
|
|
||||||
wire [31:0] mag_sq_avg;
|
wire [31:0] mag_sq_avg;
|
||||||
wire mag_sq_avg_stb;
|
wire mag_sq_avg_stb;
|
||||||
(* mark_debug = "true" *) reg [31:0] prod_thres;
|
reg [31:0] prod_thres;
|
||||||
|
|
||||||
wire [31:0] sample_delayed;
|
wire [31:0] sample_delayed;
|
||||||
wire sample_delayed_stb;
|
wire sample_delayed_stb;
|
||||||
@ -54,20 +54,28 @@ wire freq_offset_stb;
|
|||||||
|
|
||||||
reg [31:0] phase_out_neg;
|
reg [31:0] phase_out_neg;
|
||||||
|
|
||||||
(* mark_debug = "true" *) wire [31:0] delay_prod_avg_mag;
|
wire [31:0] delay_prod_avg_mag;
|
||||||
(* mark_debug = "true" *) wire delay_prod_avg_mag_stb;
|
wire delay_prod_avg_mag_stb;
|
||||||
|
|
||||||
(* mark_debug = "true" *) reg [31:0] plateau_count;
|
reg [31:0] plateau_count;
|
||||||
|
|
||||||
// this is to ensure that the short preambles contains both positive and
|
// this is to ensure that the short preambles contains both positive and
|
||||||
// negative in-phase, to avoid raise false positives when there is a constant
|
// negative in-phase, to avoid raise false positives when there is a constant
|
||||||
// power
|
// power
|
||||||
reg [31:0] pos_count;
|
reg [31:0] pos_count;
|
||||||
reg [31:0] min_pos;
|
reg [31:0] min_pos;
|
||||||
(* mark_debug = "true" *) reg has_pos;
|
reg has_pos;
|
||||||
reg [31:0] neg_count;
|
reg [31:0] neg_count;
|
||||||
reg [31:0] min_neg;
|
reg [31:0] min_neg;
|
||||||
(* mark_debug = "true" *) reg has_neg;
|
reg has_neg;
|
||||||
|
|
||||||
|
//wire [31:0] min_plateau;
|
||||||
|
|
||||||
|
// minimal number of samples that has to exceed plateau threshold to claim
|
||||||
|
// a short preamble
|
||||||
|
/*setting_reg #(.my_addr(SR_MIN_PLATEAU), .width(32), .at_reset(100)) sr_0 (
|
||||||
|
.clk(clock), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
|
||||||
|
.out(min_plateau), .changed());*/
|
||||||
|
|
||||||
|
|
||||||
complex_to_mag_sq mag_sq_inst (
|
complex_to_mag_sq mag_sq_inst (
|
||||||
|
Loading…
Reference in New Issue
Block a user