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@ -28,7 +28,7 @@ The first module in the pipeline is the :file:`power_trigger.v`. It takes the I/
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samples as input and asserts the ``trigger`` signal during a potential packet
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activity. Optionally, it can be configured to skip the first certain number of
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samples before detecting a power trigger. This is useful to skip the spurious
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signals during the intimal hardware stabilization phase.
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signals during the initial hardware stabilization phase.
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The logic of the ``power_trigger`` module is quite simple: after skipping
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certain number of initial samples, it waits for significant power increase and
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