From 23e61e6a29f899c10cb9695ef8dc1fef0c085bf7 Mon Sep 17 00:00:00 2001 From: mmehari Date: Tue, 4 Jan 2022 22:45:47 +0100 Subject: [PATCH] Avoid equalizer module processing HT_STF symbol --- verilog/dot11.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/dot11.v b/verilog/dot11.v index 00312d8..488a42e 100644 --- a/verilog/dot11.v +++ b/verilog/dot11.v @@ -371,7 +371,7 @@ equalizer equalizer_inst ( .enable(enable & equalizer_enable), .sample_in(sync_long_out), - .sample_in_strobe(sync_long_out_strobe), + .sample_in_strobe(sync_long_out_strobe && !(state==S_HT_SIGNAL && num_ofdm_symbol==6)), .ht_next(ht_next), .pkt_ht(pkt_ht), .ht_smoothing(ht_smoothing),