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fix polarity pattern

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This commit is contained in:
Jinghao Shi 2017-04-14 11:00:01 -04:00
parent 4f313f3ef9
commit 191b197d5e
1 changed files with 4 additions and 4 deletions
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8
verilog/equalizer.v
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@ -54,7 +54,7 @@ localparam HT_LTS_REF =
localparam POLARITY = localparam POLARITY =
128'b1111111000111011000101001011111010101000010110111100111001010110011000001101101011101000110010001000000100100110100111101110000; 127'b1111111000111011000101001011111010101000010110111100111001010110011000001101101011101000110010001000000100100110100111101110000;
// 21, 7, -7, -21 // 21, 7, -7, -21
localparam HT_POLARITY = 4'b1000; localparam HT_POLARITY = 4'b1000;
@ -73,7 +73,7 @@ reg [63:0] subcarrier_mask;
reg [63:0] data_subcarrier_mask; reg [63:0] data_subcarrier_mask;
reg [63:0] pilot_mask; reg [63:0] pilot_mask;
reg [127:0] polarity; reg [126:0] polarity;
reg [3:0] ht_polarity; reg [3:0] ht_polarity;
reg [3:0] current_polarity; reg [3:0] current_polarity;
reg [3:0] pilot_count; reg [3:0] pilot_count;
@ -390,7 +390,7 @@ always @(posedge clock) begin
polarity[0] // 7 polarity[0] // 7
}; };
end end
polarity <= {polarity[0], polarity[127:1]}; polarity <= {polarity[0], polarity[126:1]};
pilot_sum_i <= 0; pilot_sum_i <= 0;
pilot_sum_q <= 0; pilot_sum_q <= 0;
@ -413,7 +413,7 @@ always @(posedge clock) begin
data_subcarrier_mask <= HT_DATA_SUBCARRIER_MASK; data_subcarrier_mask <= HT_DATA_SUBCARRIER_MASK;
pilot_mask <= PILOT_MASK; pilot_mask <= PILOT_MASK;
// reverse this extra shift // reverse this extra shift
polarity <= {polarity[126:0], polarity[127]}; polarity <= {polarity[125:0], polarity[126]};
state <= S_HT_LTS; state <= S_HT_LTS;
end end