diff --git a/axi4_ip_gen.tcl b/axi4_ip_gen.tcl new file mode 100644 index 0000000..40914b6 --- /dev/null +++ b/axi4_ip_gen.tcl @@ -0,0 +1,454 @@ +#***************************************************************************************** +# Vivado (TM) v2017.4.1 (64-bit) +# +# ip_gen_test1.tcl: Tcl script for re-creating project 'edit_power_trigger_axi4_v1_0' +# +# Generated by Vivado on Mon Jan 21 11:32:41 +0100 2019 +# IP Build 2095745 on Tue Jan 30 17:13:15 MST 2018 +# +# This file contains the Vivado Tcl commands for re-creating the project to the state* +# when this script was generated. In order to re-create the project, please source this +# file in the Vivado Tcl Shell. +# +# * Note that the runs in the created project will be configured the same way as the +# original project, however they will not be launched automatically. To regenerate the +# run results please launch the synthesis/implementation runs as needed. +# +#***************************************************************************************** +# NOTE: In order to use this script for source control purposes, please make sure that the +# following files are added to the source control system:- +# +# 1. This project restoration tcl script (ip_gen_test1.tcl) that was generated. +# +# 2. The following source(s) files that were local or imported into the original project. +# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) +# +# "C:/Users/lwei/Downloads/ip_repo-20190121T095109Z-001/ip_repo/power_trigger_axi4_1.0/src/delayT.v" +# "C:/Users/lwei/Downloads/ip_repo-20190121T095109Z-001/ip_repo/power_trigger_axi4_1.0/src/power_trigger.v" +# "C:/Users/lwei/Downloads/ip_repo-20190121T095109Z-001/ip_repo/power_trigger_axi4_1.0/hdl/power_trigger_axi4_v1_0_S00_AXI.v" +# "C:/Users/lwei/Downloads/ip_repo-20190121T095109Z-001/ip_repo/power_trigger_axi4_1.0/hdl/power_trigger_axi4_v1_0.v" +# "C:/Users/lwei/Downloads/ip_repo-20190121T095109Z-001/ip_repo/power_trigger_axi4_1.0/component.xml" +# +# 3. The following remote source files that were added to the original project:- +# +# +# +#***************************************************************************************** + +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir [file dirname [info script]] + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set project_name "edit_dot11_axi4_ip" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set project_name $::user_project_name +} + +variable script_file +set script_file "axi4_ip_gen.tcl" + +# Help information for this script +proc help {} { + variable script_file + puts "\nDescription:" + puts "Recreate a Vivado project from this script. The created project will be" + puts "functionally equivalent to the original project for which this script was" + puts "generated. The script contains commands for creating a project, filesets," + puts "runs, adding/importing sources and setting properties on various objects.\n" + puts "Syntax:" + puts "$script_file" + puts "$script_file -tclargs \[--origin_dir \]" + puts "$script_file -tclargs \[--project_name \]" + puts "$script_file -tclargs \[--help\]\n" + puts "Usage:" + puts "Name Description" + puts "-------------------------------------------------------------------------" + puts "\[--origin_dir \] Determine source file paths wrt this path. Default" + puts " origin_dir path value is \".\", otherwise, the value" + puts " that was set with the \"-paths_relative_to\" switch" + puts " when this script was generated.\n" + puts "\[--project_name \] Create project with the specified name. Default" + puts " name is the name of the project from where this" + puts " script was generated.\n" + puts "\[--help\] Print help information for this script" + puts "-------------------------------------------------------------------------\n" + exit 0 +} + +if { $::argc > 0 } { + for {set i 0} {$i < [llength $::argc]} {incr i} { + set option [string trim [lindex $::argv $i]] + switch -regexp -- $option { + "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } + "--project_name" { incr i; set project_name [lindex $::argv $i] } + "--help" { help } + default { + if { [regexp {^-} $option] } { + puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" + return 1 + } + } + } + } +} + +# Set the directory path for the original project from where this script was exported +set src_dir "[file normalize "$origin_dir/verilog"]" + +# Create project +create_project ${project_name} ./${project_name} -part xc7z045ffg900-2 + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Reconstruct message rules +# None + +# Set project properties +set obj [current_project] +set_property -name "board_part" -value "xilinx.com:zc706:part0:1.4" -objects $obj +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "dsa.num_compute_units" -value "60" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_output_repo" -value "$proj_dir/${project_name}.cache/ip" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj +set_property -name "xpm_libraries" -value "XPM_MEMORY" -objects $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set IP repository paths +set obj [get_filesets sources_1] + +# Rebuild user ip_repo's index before adding any source files +#update_ip_catalog -rebuild + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +# Import local files from the original project +set files [list \ + "[file normalize "$origin_dir/verilog/Xilinx/vivado2017.4.1/viterbi/viterbi_v7_0.xci"]"\ + "[file normalize "$origin_dir/verilog/Xilinx/vivado2017.4.1/deinter_lut/deinter_lut.xci"]"\ + "[file normalize "$origin_dir/verilog/coregen/div_gen_v3_0.ngc"]"\ + "[file normalize "$origin_dir/verilog/Xilinx/vivado2017.4.1/complex_multiplier/complex_multiplier.xci"]"\ + "[file normalize "$origin_dir/verilog/Xilinx/vivado2017.4.1/xfft/xfft_v9.xci"]"\ + "[file normalize "$origin_dir/verilog/Xilinx/vivado2017.4.1/atan_lut/atan_lut.xci"]"\ + "[file normalize "$origin_dir/verilog/Xilinx/vivado2017.4.1/rot_lut/rot_lut.xci"]"\ + "[file normalize "$origin_dir/verilog/bits_to_bytes.v"]"\ + "[file normalize "$origin_dir/verilog/calc_mean.v"]"\ + "[file normalize "$origin_dir/verilog/complex_mult.v"]"\ + "[file normalize "$origin_dir/verilog/complex_to_mag.v"]"\ + "[file normalize "$origin_dir/verilog/complex_to_mag_sq.v"]"\ + "[file normalize "$origin_dir/verilog/crc32.v"]"\ + "[file normalize "$origin_dir/verilog/deinterleave.v"]"\ + "[file normalize "$origin_dir/verilog/delayT.v"]"\ + "[file normalize "$origin_dir/verilog/delay_sample.v"]"\ + "[file normalize "$origin_dir/verilog/common_defs.v"]"\ + "[file normalize "$origin_dir/verilog/demodulate.v"]"\ + "[file normalize "$origin_dir/verilog/descramble.v"]"\ + "[file normalize "$origin_dir/verilog/coregen/div_gen_v3_0.v"]"\ + "[file normalize "$origin_dir/verilog/divider.v"]"\ + "[file normalize "$origin_dir/verilog/dot11.v"]"\ + "[file normalize "$origin_dir/verilog/equalizer.v"]"\ + "[file normalize "$origin_dir/verilog/ht_sig_crc.v"]"\ + "[file normalize "$origin_dir/verilog/moving_avg.v"]"\ + "[file normalize "$origin_dir/verilog/ofdm_decoder.v"]"\ + "[file normalize "$origin_dir/verilog/phase.v"]"\ + "[file normalize "$origin_dir/verilog/power_trigger.v"]"\ + "[file normalize "$origin_dir/verilog/dot11zynq_S00_AXI.v"]"\ + "[file normalize "$origin_dir/verilog/usrp2/ram_2port.v"]"\ + "[file normalize "$origin_dir/verilog/rotate.v"]"\ + "[file normalize "$origin_dir/verilog/stage_mult.v"]"\ + "[file normalize "$origin_dir/verilog/sync_long.v"]"\ + "[file normalize "$origin_dir/verilog/sync_short.v"]"\ + "[file normalize "$origin_dir/verilog/dot11zynq.v"]"\ + "[file normalize "$origin_dir/verilog/Xilinx/vivado2017.4.1/deinter_lut/deinter_lut.coe"]"\ + "[file normalize "$origin_dir/verilog/Xilinx/vivado2017.4.1/atan_lut/atan_lut.coe"]"\ + "[file normalize "$origin_dir/verilog/Xilinx/vivado2017.4.1/rot_lut/rot_lut.coe"]"\ + "[file normalize "$origin_dir/verilog/intf_64bit.v"]"\ +] +# If you want to make a copy of the file to new src folder, use following command +# set imported_files [import_files -fileset sources_1 $files] +# If you want to keep the files remote, use the following command +# set added_files [add_files -fileset sources_1 $files] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/verilog/coregen/div_gen_v3_0.ngc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "NGC" -objects $file_obj + +set file "dot11zynq_S00_AXI.v" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "used_in" -value "synthesis simulation" -objects $file_obj +set_property -name "used_in_implementation" -value "0" -objects $file_obj + +set file "dot11zynq.v" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "used_in" -value "synthesis simulation" -objects $file_obj +set_property -name "used_in_implementation" -value "0" -objects $file_obj + + +# Set 'sources_1' fileset file properties for local files + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "top" -value "dot11zynq" -objects $obj + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Empty (no sources present) + + +# Create constraints ! +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] + +# Create runs +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Set 'sim_1' fileset object +set obj [get_filesets sim_1] +set files [list \ + "[file normalize "$origin_dir/verilog/dot11_tb.v"]"\ +] +add_files -norecurse -fileset $obj $files +# Empty (no sources present) + +# Set 'sim_1' fileset properties +set obj [get_filesets sim_1] +set_property -name "top" -value "dot11_tb" -objects $obj + +# Create 'synth_1' run (if not found) +if {[string equal [get_runs -quiet synth_1] ""]} { + create_run -name synth_1 -part xc7z045ffg900-2 -flow {Vivado Synthesis 2017} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] + set_property flow "Vivado Synthesis 2017" [get_runs synth_1] +} +set obj [get_runs synth_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Synthesis Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'synth_1_synth_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } { + create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1 +} +set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] +if { $obj != "" } { + +} +set obj [get_runs synth_1] +set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj + +# set the current synth run +current_run -synthesis [get_runs synth_1] + +# Create 'impl_1' run (if not found) +if {[string equal [get_runs -quiet impl_1] ""]} { + create_run -name impl_1 -part xc7z045ffg900-2 -flow {Vivado Implementation 2017} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] + set_property flow "Vivado Implementation 2017" [get_runs impl_1] +} +set obj [get_runs impl_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Implementation Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'impl_1_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { + create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { + create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { + create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] +if { $obj != "" } { + +} +set obj [get_runs impl_1] +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj + +# set the current impl run +current_run -implementation [get_runs impl_1] + +puts "INFO: Project created:$project_name" diff --git a/verilog/Xilinx/vivado2017.4.1/atan_lut/atan_lut.coe b/verilog/Xilinx/vivado2017.4.1/atan_lut/atan_lut.coe new file mode 100644 index 0000000..d764cb3 --- /dev/null +++ b/verilog/Xilinx/vivado2017.4.1/atan_lut/atan_lut.coe @@ -0,0 +1,258 @@ +memory_initialization_radix=2; +memory_initialization_vector= +000000000, +000000010, +000000100, +000000110, +000001000, +000001010, +000001100, +000001110, +000010000, +000010010, +000010100, +000010110, +000011000, +000011010, +000011100, +000011110, +000100000, +000100010, +000100100, +000100110, +000101000, +000101010, +000101100, +000101110, +000110000, +000110010, +000110100, +000110110, +000111000, +000111010, +000111100, +000111110, +001000000, +001000010, +001000100, +001000110, +001001000, +001001001, +001001011, +001001101, +001001111, +001010001, +001010011, +001010101, +001010111, +001011001, +001011011, +001011101, +001011111, +001100001, +001100011, +001100101, +001100111, +001101001, +001101010, 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1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + READ_WRITE + OTHER + NONE + 8192 + 32 + READ_WRITE + + 100000000 + 0.000 + 8 + 8 + 1 + 4 + 0 + 1 + 9 + 0 + 1 + 0 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 2.4184000000000001 mW + zynq + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + atan_lut.mem + atan_lut.mif + 0 + 1 + 3 + 0 + 1 + 256 + 256 + 9 + 9 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 256 + 256 + WRITE_FIRST + WRITE_FIRST + 9 + 9 + zynq + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + atan_lut.coe + ALL + atan_lut + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + true + no_mem_loaded + Single_Port_ROM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 0 + 0 + 0 + 0 + 8kx2 + false + false + 9 + 9 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 256 + 9 + 9 + No_ECC + false + false + false + Stand_Alone + zynq + xilinx.com:zc706:part0:1.4 + xc7z045 + ffg900 + VERILOG + + MIXED + -2 + + TRUE + TRUE + IP_Flow + 1 + TRUE + . + + . + 2017.4.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/Xilinx/vivado2017.4.1/complex_multiplier/complex_multiplier.xci b/verilog/Xilinx/vivado2017.4.1/complex_multiplier/complex_multiplier.xci new file mode 100644 index 0000000..36b9958 --- /dev/null +++ b/verilog/Xilinx/vivado2017.4.1/complex_multiplier/complex_multiplier.xci @@ -0,0 +1,173 @@ + + + xilinx.com + xci + unknown + 1.0 + + + complex_multiplier + + + ACTIVE_LOW + + 10000000 + 0.000 + + 100000000 + 0 + 0 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 16 + 16 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 1 + 64 + 1 + 1 + 32 + 32 + 1 + 32 + 1 + 8 + 1 + 3 + 0 + 0 + xc7z045 + zynq + 0 + 0 + 0 + 1 + false + 16 + false + 1 + 16 + 1 + 1 + complex_multiplier + NonBlocking + false + false + false + false + false + false + Manual + 3 + Use_Mults + Performance + Null + 32 + Truncate + zynq + xilinx.com:zc706:part0:1.4 + xc7z045 + ffg900 + VERILOG + + MIXED + -2 + + TRUE + TRUE + IP_Flow + 14 + TRUE + . + + . + 2017.4 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/Xilinx/vivado2017.4.1/deinter_lut/deinter_lut.coe b/verilog/Xilinx/vivado2017.4.1/deinter_lut/deinter_lut.coe new file mode 100644 index 0000000..d28e76a --- /dev/null +++ b/verilog/Xilinx/vivado2017.4.1/deinter_lut/deinter_lut.coe @@ -0,0 +1,2050 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0000000000000000000000, +0000000000000000000000, +0000000000000000000000, +0000000000000000000000, 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+0000000000000000000000, +0000000000000000000000, +0000000000000000000000, +0000000000000000000000; \ No newline at end of file diff --git a/verilog/Xilinx/vivado2017.4.1/deinter_lut/deinter_lut.xci b/verilog/Xilinx/vivado2017.4.1/deinter_lut/deinter_lut.xci new file mode 100644 index 0000000..ed00e73 --- /dev/null +++ b/verilog/Xilinx/vivado2017.4.1/deinter_lut/deinter_lut.xci @@ -0,0 +1,268 @@ + + + xilinx.com + xci + unknown + 1.0 + + + deinter_lut + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + READ_WRITE + OTHER + NONE + 8192 + 32 + READ_WRITE + + 100000000 + 0.000 + 11 + 11 + 1 + 4 + 0 + 1 + 9 + 0 + 1 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 3.6199499999999998 mW + zynq + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + deinter_lut.mem + deinter_lut.mif + 0 + 1 + 3 + 0 + 1 + 2048 + 2048 + 22 + 22 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 2048 + 2048 + WRITE_FIRST + WRITE_FIRST + 22 + 22 + zynq + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + deinter_lut.coe + ALL + deinter_lut + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + true + no_mem_loaded + Single_Port_ROM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 0 + 0 + 0 + 0 + 8kx2 + false + false + 22 + 22 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 2048 + 22 + 22 + No_ECC + false + false + false + Stand_Alone + zynq + xilinx.com:zc706:part0:1.4 + xc7z045 + ffg900 + VERILOG + + MIXED + -2 + + TRUE + TRUE + IP_Flow + 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4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + READ_WRITE + OTHER + NONE + 8192 + 32 + READ_WRITE + + 100000000 + 0.000 + 9 + 9 + 1 + 4 + 0 + 1 + 9 + 1 + 0 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 5.244 mW + zynq + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + rot_lut.mem + rot_lut.mif + 0 + 1 + 4 + 0 + 1 + 512 + 512 + 32 + 32 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 512 + 512 + WRITE_FIRST + WRITE_FIRST + 32 + 32 + zynq + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + true + 9 + NONE + rot_lut.coe + ALL + rot_lut + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + true + no_mem_loaded + Dual_Port_ROM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 0 + 100 + 100 + 0 + 8kx2 + false + false + 32 + 32 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 512 + 32 + 32 + No_ECC + false + false + false + Stand_Alone + zynq + xilinx.com:zc706:part0:1.4 + xc7z045 + ffg900 + VERILOG + + MIXED + -2 + + TRUE + TRUE + IP_Flow + 1 + TRUE + . + + . + 2017.4.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/Xilinx/vivado2017.4.1/viterbi/viterbi_v7_0.xci b/verilog/Xilinx/vivado2017.4.1/viterbi/viterbi_v7_0.xci new file mode 100644 index 0000000..7ac0869 --- /dev/null +++ b/verilog/Xilinx/vivado2017.4.1/viterbi/viterbi_v7_0.xci @@ -0,0 +1,214 @@ + + + xilinx.com + xci + unknown + 1.0 + + + viterbi_v7_0 + + + ACTIVE_LOW + + 100000000 + 0.000 + + 100000000 + 0 + 0 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 2 + 0 + 0 + 8 + + 100000000 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 3 + 1 + viterbi_v7_0 + 7 + 91 + 121 + 0 + 0 + 0 + 0 + 0 + 121 + 91 + 0 + 0 + 0 + 0 + 0 + 0 + ./ + 1 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 8 + 1 + 16 + 2 + 2 + 1 + 0 + 0 + 1 + 3 + 16 + 8 + 16 + 24 + 0 + zynq + true + Parallel + false + true + 3 + false + 1 + Soft_Coding + viterbi_v7_0 + 7 + 133 + 171 + 0 + 0 + 0 + 0 + 0 + 1111001 + 1011011 + 0 + 0 + 0 + 0 + 0 + Octal + Binary + Signed_Magnitude + false + 2 + 2 + External + true + 3 + false + 24 + Standard + zynq + xilinx.com:zc706:part0:1.4 + xc7z045 + ffg900 + VERILOG + + MIXED + -2 + + TRUE + TRUE + IP_Flow + 8 + TRUE + . + + . + 2017.4.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/Xilinx/vivado2017.4.1/xfft/xfft_v9.xci b/verilog/Xilinx/vivado2017.4.1/xfft/xfft_v9.xci new file mode 100644 index 0000000..82d03ae --- /dev/null +++ b/verilog/Xilinx/vivado2017.4.1/xfft/xfft_v9.xci @@ -0,0 +1,195 @@ + + + xilinx.com + xci + unknown + 1.0 + + + xfft_v7_1 + + + ACTIVE_LOW + + 100000000 + 0.000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 1 + 0 + undef + 0.000 + 6 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + 3 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 16 + 48 + 1 + 1 + 6 + 0 + 23 + 1 + 8 + 32 + 1 + 1 + 16 + 0 + 0 + zynq + xfft_v7_1 + false + true + use_luts + 1 + use_mults_resources + false + fixed_point + pipelined_streaming_io + 16 + block_ram + false + block_ram + block_ram + 1 + natural_order + false + 16 + truncation + false + unscaled + 100 + 50 + nonrealtime + 64 + false + zynq + xilinx.com:zc706:part0:1.4 + xc7z045 + ffg900 + VERILOG + + MIXED + -2 + + TRUE + TRUE + IP_Flow + 14 + TRUE + . + + . + 2017.4.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/complex_mult.v b/verilog/complex_mult.v index 82d1495..f622db1 100644 --- a/verilog/complex_mult.v +++ b/verilog/complex_mult.v @@ -26,14 +26,25 @@ reg [15:0] bi; wire [31:0] prod_i; wire [31:0] prod_q; + +// instantiation of complex multiplier +wire [31:0] s_axis_a_tdata; +assign s_axis_a_tdata = {ai,ar} ; +wire [31:0] s_axis_b_tdata; +assign s_axis_b_tdata = {bi, br} ; +wire [63:0] m_axis_dout_tdata; +assign prod_q = m_axis_dout_tdata[63:32]; +assign prod_i = m_axis_dout_tdata[31:0]; +wire m_axis_dout_tvalid ; // first try not use it + complex_multiplier mult_inst ( - .clk(clock), - .ar(ar), - .ai(ai), - .br(br), - .bi(bi), - .pr(prod_i), - .pi(prod_q) + .aclk(clock), // input wire aclk + .s_axis_a_tvalid(input_strobe), // input wire s_axis_a_tvalid + .s_axis_a_tdata(s_axis_a_tdata), // input wire [31 : 0] s_axis_a_tdata + .s_axis_b_tvalid(input_strobe), // input wire s_axis_b_tvalid + .s_axis_b_tdata(s_axis_b_tdata), // input wire [31 : 0] s_axis_b_tdata + .m_axis_dout_tvalid(m_axis_dout_tvalid), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata(m_axis_dout_tdata) // output wire [63 : 0] m_axis_dout_tdata ); delayT #(.DATA_WIDTH(1), .DELAY(5)) stb_delay_inst ( diff --git a/verilog/dot11.v b/verilog/dot11.v index 6516dbd..8677abc 100644 --- a/verilog/dot11.v +++ b/verilog/dot11.v @@ -6,9 +6,16 @@ module dot11 ( input reset, // setting registers - input set_stb, - input [7:0] set_addr, - input [31:0] set_data, + //input set_stb, + //input [7:0] set_addr, + //input [31:0] set_data, + + // add ports for register based inputs + input [15:0] power_thres, + input [15:0] window_size, + input [31:0] num_sample_to_skip, + input num_sample_changed, + input [31:0] min_plateau, // INPUT: I/Q sample input [31:0] sample_in, @@ -23,6 +30,8 @@ module dot11 ( output [7:0] byte_out, output reg fcs_out_strobe, output reg fcs_ok, + output wire [63:0] data_out, + output wire data_out_valid, ///////////////////////////////////////////////////////// // DEBUG PORTS @@ -35,6 +44,7 @@ module dot11 ( // power trigger output power_trigger, + output [1:0] pw_state_spy, // sync short output short_preamble_detected, @@ -61,6 +71,8 @@ module dot11 ( output legacy_sig_parity, output legacy_sig_parity_ok, output [5:0] legacy_sig_tail, + output [23:0] sig_bits_spy, + output [31:0] byte_count_spy, // ht signal info output reg ht_sig_stb, @@ -160,10 +172,10 @@ phase phase_inst ( //////////////////////////////////////////////////////////////////////////////// -reg sync_short_reset; -reg sync_long_reset; -wire sync_short_enable = state == S_SYNC_SHORT; -reg sync_long_enable; +(* mark_debug = "true" *) reg sync_short_reset; +(* mark_debug = "true" *) reg sync_long_reset; +(* mark_debug = "true" *) wire sync_short_enable = state == S_SYNC_SHORT; +(* mark_debug = "true" *) reg sync_long_enable; reg equalizer_reset; reg equalizer_enable; @@ -197,6 +209,8 @@ assign state_changed = state != old_state; // SIGNAL information reg [23:0] signal_bits; reg [31:0] byte_count; +assign sig_bits_spy = signal_bits; +assign byte_count_spy = byte_count ; assign legacy_rate = signal_bits[3:0]; assign legacy_sig_rsvd = signal_bits[4]; @@ -262,10 +276,12 @@ power_trigger power_trigger_inst ( .sample_in(sample_in), .sample_in_strobe(sample_in_strobe), - .set_stb(set_stb), - .set_addr(set_addr), - .set_data(set_data), + .power_thres(power_thres), + .window_size(window_size), + .num_sample_to_skip(num_sample_to_skip), + .num_sample_changed(num_sample_changed), + .pw_state_spy(pw_state_spy), .trigger(power_trigger) ); @@ -274,10 +290,7 @@ sync_short sync_short_inst ( .reset(reset | sync_short_reset), .enable(enable & sync_short_enable), - .set_stb(set_stb), - .set_addr(set_addr), - .set_data(set_data), - + .min_plateau(min_plateau), .sample_in(sample_in), .sample_in_strobe(sample_in_strobe), @@ -297,10 +310,6 @@ sync_long sync_long_inst ( .reset(reset | sync_long_reset), .enable(enable & sync_long_enable), - .set_stb(set_stb), - .set_addr(set_addr), - .set_data(set_data), - .sample_in(sample_in), .sample_in_strobe(sample_in_strobe), .phase_offset(phase_offset), @@ -399,6 +408,21 @@ crc32 fcs_inst ( .crc_out(pkt_fcs) ); +intf_64bit intf64bit_inst ( + .clock(clock), + .reset(reset | sync_short_reset), + .enable(enable), + .pkt_len(pkt_len), + .byte_index(byte_count), + + .byte_in(byte_out), + .byte_strobe(byte_out_strobe), + + .data_out(data_out), + .output_strobe(data_out_valid) +); + + always @(posedge clock) begin if (reset) begin @@ -817,6 +841,7 @@ always @(posedge clock) begin end `endif fcs_out_strobe <= 0; + fcs_ok <= 0 ; state <= S_WAIT_POWER_TRIGGER; end diff --git a/verilog/dot11_tb.v b/verilog/dot11_tb.v index 88a86c5..56f0769 100644 --- a/verilog/dot11_tb.v +++ b/verilog/dot11_tb.v @@ -40,9 +40,11 @@ wire descramble_out_strobe; wire [3:0] legacy_rate; wire legacy_sig_rsvd; wire [11:0] legacy_len; -wire legacy_sig_parity; +wire legacy_sig_parity, legacy_sig_parity_ok; wire [5:0] legacy_sig_tail; wire legacy_sig_stb; +wire [23:0] sig_bits_spy; +wire [31:0] byte_count_spy; reg signal_done; wire [3:0] dot11_state; @@ -50,11 +52,17 @@ wire [3:0] dot11_state; wire [7:0] byte_out; wire byte_out_strobe; +wire [63:0] data_out ; +wire data_out_valid ; + reg set_stb; reg [7:0] set_addr; reg [31:0] set_data; + +wire fcs_out_strobe, fcs_ok; + localparam RAM_SIZE = 1<<25; reg [31:0] ram [0:RAM_SIZE-1]; @@ -79,6 +87,11 @@ integer signal_fd; integer byte_out_fd; +integer fcs_fd ; + + // spy ports added (lwei) +wire [1:0] pw_state_spy; + `ifndef SAMPLE_FILE `define SAMPLE_FILE "../testing_inputs/conducted/dot11a_24mbps_qos_data_e4_90_7e_15_2a_16_e8_de_27_90_6e_42.txt" `endif @@ -131,6 +144,9 @@ initial begin signal_fd = $fopen("./sim_out/signal_out.txt", "w"); byte_out_fd = $fopen("./sim_out/byte_out.txt", "w"); + + fcs_fd = $fopen("./sim_out/fcs_out.txt", "w"); + //# 50100; enable = 0 ; end @@ -227,6 +243,11 @@ always @(posedge clock) begin $fflush(byte_out_fd); end + if (fcs_out_strobe) begin + $fwrite(fcs_fd, "%d\n", fcs_ok); + $fflush(fcs_fd); + end + end end @@ -234,17 +255,20 @@ dot11 dot11_inst ( .clock(clock), .reset(reset), .enable(enable), - - .set_addr(set_addr), - .set_stb(set_stb), - .set_data(set_data), - .sample_in(sample_in), .sample_in_strobe(sample_in_strobe), - + //.set_addr(set_addr), + //.set_stb(set_stb), + //.set_data(set_data), + .power_thres(16'd100), + .window_size(16'd80), + .num_sample_to_skip(32'd10), + .num_sample_changed(1'b0), + .min_plateau(32'd100), .state(dot11_state), .power_trigger(power_trigger), + .pw_state_spy(pw_state_spy), .short_preamble_detected(short_preamble_detected), .sync_long_metric(sync_long_metric), @@ -271,13 +295,22 @@ dot11 dot11_inst ( .byte_out(byte_out), .byte_out_strobe(byte_out_strobe), + + .data_out(data_out), + .data_out_valid(data_out_valid), .legacy_rate(legacy_rate), .legacy_sig_rsvd(legacy_sig_rsvd), .legacy_len(legacy_len), .legacy_sig_parity(legacy_sig_parity), + .legacy_sig_parity_ok(legacy_sig_parity_ok), .legacy_sig_tail(legacy_sig_tail), - .legacy_sig_stb(legacy_sig_stb) + .legacy_sig_stb(legacy_sig_stb), + .sig_bits_spy(sig_bits_spy), + .byte_count_spy(byte_count_spy), + + .fcs_out_strobe(fcs_out_strobe), + .fcs_ok(fcs_ok) ); endmodule diff --git a/verilog/dot11zynq.v b/verilog/dot11zynq.v new file mode 100644 index 0000000..dafda85 --- /dev/null +++ b/verilog/dot11zynq.v @@ -0,0 +1,132 @@ + +`timescale 1 ns / 1 ps + + module dot11zynq # + ( + // Users to add parameters here + + // User parameters ends + // Do not modify the parameters beyond this line + + + // Parameters of Axi Slave Bus Interface S00_AXI + parameter integer C_S00_AXI_DATA_WIDTH = 32, + parameter integer C_S00_AXI_ADDR_WIDTH = 7 + ) + ( + // Users to add ports here + + // User ports ends + // Do not modify the ports beyond this line + input wire enable, + input wire [31:0] sample_in, + input wire sample_in_strobe, + output wire trigger, + + output wire ofdm_byte_valid, + output wire [7:0] ofdm_byte, + output wire [63:0] data_out, + output wire data_out_valid, + output wire fcs_valid, + output wire fcs_invalid, + + output wire sig_valid, + output wire sig_invalid, + output wire [2:0] mcs_io, + output wire [11:0] pkt_len_io, + + output wire [6:0] ht_mcs_io, + output wire [15:0] ht_pkt_len_io, + output wire ht_sig_invalid, + output wire ht_sig_valid, + output wire ht_unsupported, + + + // ports to interract with fifo + input wire fifo_empty, + output wire rd_en, + output wire fifo_rst, + // Ports of Axi Slave Bus Interface S00_AXI + input wire s00_axi_aclk, + input wire s00_axi_aresetn, + input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr, + input wire [2 : 0] s00_axi_awprot, + input wire s00_axi_awvalid, + output wire s00_axi_awready, + input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata, + input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb, + input wire s00_axi_wvalid, + output wire s00_axi_wready, + output wire [1 : 0] s00_axi_bresp, + output wire s00_axi_bvalid, + input wire s00_axi_bready, + input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr, + input wire [2 : 0] s00_axi_arprot, + input wire s00_axi_arvalid, + output wire s00_axi_arready, + output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata, + output wire [1 : 0] s00_axi_rresp, + output wire s00_axi_rvalid, + input wire s00_axi_rready + ); +// Instantiation of Axi Bus Interface S00_AXI + dot11zynq_S00_AXI # ( + .C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH), + .C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH) + ) dot11zynq_S00_AXI_inst ( + // user ports + .enable(enable), + .sample_in(sample_in), + .sample_in_strobe(sample_in_strobe), + .trigger(trigger), + + .ofdm_byte_valid(ofdm_byte_valid), + .ofdm_byte(ofdm_byte), + .data_out(data_out), + .data_out_valid(data_out_valid), + .fcs_valid(fcs_valid), + .fcs_invalid(fcs_invalid), + + .sig_valid(sig_valid), + .sig_invalid(sig_invalid), + .mcs_io(mcs_io), + .pkt_len_io(pkt_len_io), + + .ht_mcs_io(ht_mcs_io), + .ht_pkt_len_io(ht_pkt_len_io), + .ht_sig_invalid(ht_sig_invalid), + .ht_sig_valid(ht_sig_valid), + .ht_unsupported(ht_unsupported), + + .fifo_empty(fifo_empty), + .rd_en(rd_en), + .fifo_rst(fifo_rst), + // user ports end + .S_AXI_ACLK(s00_axi_aclk), + .S_AXI_ARESETN(s00_axi_aresetn), + .S_AXI_AWADDR(s00_axi_awaddr), + .S_AXI_AWPROT(s00_axi_awprot), + .S_AXI_AWVALID(s00_axi_awvalid), + .S_AXI_AWREADY(s00_axi_awready), + .S_AXI_WDATA(s00_axi_wdata), + .S_AXI_WSTRB(s00_axi_wstrb), + .S_AXI_WVALID(s00_axi_wvalid), + .S_AXI_WREADY(s00_axi_wready), + .S_AXI_BRESP(s00_axi_bresp), + .S_AXI_BVALID(s00_axi_bvalid), + .S_AXI_BREADY(s00_axi_bready), + .S_AXI_ARADDR(s00_axi_araddr), + .S_AXI_ARPROT(s00_axi_arprot), + .S_AXI_ARVALID(s00_axi_arvalid), + .S_AXI_ARREADY(s00_axi_arready), + .S_AXI_RDATA(s00_axi_rdata), + .S_AXI_RRESP(s00_axi_rresp), + .S_AXI_RVALID(s00_axi_rvalid), + .S_AXI_RREADY(s00_axi_rready) + ); + + // Add user logic here + + // User logic ends + + endmodule diff --git a/verilog/dot11zynq_S00_AXI.v b/verilog/dot11zynq_S00_AXI.v new file mode 100644 index 0000000..9f99f0b --- /dev/null +++ b/verilog/dot11zynq_S00_AXI.v @@ -0,0 +1,953 @@ + +`timescale 1 ns / 1 ps + + module dot11zynq_S00_AXI # + ( + // Users to add parameters here + + // User parameters ends + // Do not modify the parameters beyond this line + + // Width of S_AXI data bus + parameter integer C_S_AXI_DATA_WIDTH = 32, + // Width of S_AXI address bus + parameter integer C_S_AXI_ADDR_WIDTH = 7 + ) + ( + // Users to add ports here + input wire enable, + input wire [31:0] sample_in, + input wire sample_in_strobe, + + output wire trigger, + output wire ofdm_byte_valid, + output wire [7:0] ofdm_byte, + output wire [63:0] data_out, // only has payload, doesn't have signal + output wire data_out_valid, + output wire fcs_valid, + output wire fcs_invalid, + + output wire sig_valid, + output wire sig_invalid, + output reg [2:0] mcs_io, + output wire [11:0] pkt_len_io, + + output wire [6:0] ht_mcs_io, + output wire [15:0] ht_pkt_len_io, + output wire ht_sig_invalid, + output wire ht_sig_valid, + output reg ht_unsupported, + + // ports to interract with fifo + input wire fifo_empty, + output reg rd_en, + output wire fifo_rst, + // User ports ends + // Do not modify the ports beyond this line + + // Global Clock Signal + input wire S_AXI_ACLK, + // Global Reset Signal. This Signal is Active LOW + input wire S_AXI_ARESETN, + // Write address (issued by master, acceped by Slave) + input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR, + // Write channel Protection type. This signal indicates the + // privilege and security level of the transaction, and whether + // the transaction is a data access or an instruction access. + input wire [2 : 0] S_AXI_AWPROT, + // Write address valid. This signal indicates that the master signaling + // valid write address and control information. + input wire S_AXI_AWVALID, + // Write address ready. This signal indicates that the slave is ready + // to accept an address and associated control signals. + output wire S_AXI_AWREADY, + // Write data (issued by master, acceped by Slave) + input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA, + // Write strobes. This signal indicates which byte lanes hold + // valid data. There is one write strobe bit for each eight + // bits of the write data bus. + input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB, + // Write valid. This signal indicates that valid write + // data and strobes are available. + input wire S_AXI_WVALID, + // Write ready. This signal indicates that the slave + // can accept the write data. + output wire S_AXI_WREADY, + // Write response. This signal indicates the status + // of the write transaction. + output wire [1 : 0] S_AXI_BRESP, + // Write response valid. This signal indicates that the channel + // is signaling a valid write response. + output wire S_AXI_BVALID, + // Response ready. This signal indicates that the master + // can accept a write response. + input wire S_AXI_BREADY, + // Read address (issued by master, acceped by Slave) + input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR, + // Protection type. This signal indicates the privilege + // and security level of the transaction, and whether the + // transaction is a data access or an instruction access. + input wire [2 : 0] S_AXI_ARPROT, + // Read address valid. This signal indicates that the channel + // is signaling valid read address and control information. + input wire S_AXI_ARVALID, + // Read address ready. This signal indicates that the slave is + // ready to accept an address and associated control signals. + output wire S_AXI_ARREADY, + // Read data (issued by slave) + output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA, + // Read response. This signal indicates the status of the + // read transfer. + output wire [1 : 0] S_AXI_RRESP, + // Read valid. This signal indicates that the channel is + // signaling the required read data. + output wire S_AXI_RVALID, + // Read ready. This signal indicates that the master can + // accept the read data and response information. + input wire S_AXI_RREADY + ); + + // AXI4LITE signals + reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr; + reg axi_awready; + reg axi_wready; + reg [1 : 0] axi_bresp; + reg axi_bvalid; + reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr; + reg axi_arready; + reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata; + reg [1 : 0] axi_rresp; + reg axi_rvalid; + + // Example-specific design signals + // local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + // ADDR_LSB is used for addressing 32/64 bit registers/memories + // ADDR_LSB = 2 for 32 bits (n downto 2) + // ADDR_LSB = 3 for 64 bits (n downto 3) + localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1; + localparam integer OPT_MEM_ADDR_BITS = 4; + + // openofdm local parameters for ht signal condition + // erros in HT-SIGNAL + localparam E_UNSUPPORTED_MCS = 1; + localparam E_UNSUPPORTED_CBW = 2; + localparam E_HT_WRONG_RSVD = 3; + localparam E_UNSUPPORTED_STBC = 4; + localparam E_UNSUPPORTED_FEC = 5; + localparam E_UNSUPPORTED_SGI = 6; + localparam E_UNSUPPORTED_SPATIAL = 7; + localparam E_HT_WRONG_TAIL = 8; + localparam E_WRONG_CRC = 9; + + //---------------------------------------------- + //-- Signals for user logic register space example + //------------------------------------------------ + //-- Number of Slave Registers 32 + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg9; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg10; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg11; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg12; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg13; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg14; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg15; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg17; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg18; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg19; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg20; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg21; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg22; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg23; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg24; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg25; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg26; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg27; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31; + wire slv_reg_rden; + wire slv_reg_wren; + reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out; + integer byte_index; + reg aw_en; + + // I/O Connections assignments + + assign S_AXI_AWREADY = axi_awready; + assign S_AXI_WREADY = axi_wready; + assign S_AXI_BRESP = axi_bresp; + assign S_AXI_BVALID = axi_bvalid; + assign S_AXI_ARREADY = axi_arready; + assign S_AXI_RDATA = axi_rdata; + assign S_AXI_RRESP = axi_rresp; + assign S_AXI_RVALID = axi_rvalid; + // Implement axi_awready generation + // axi_awready is asserted for one S_AXI_ACLK clock cycle when both + // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + // de-asserted when reset is low. + + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + axi_awready <= 1'b0; + aw_en <= 1'b1; + end + else + begin + if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en) + begin + // slave is ready to accept write address when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_awready <= 1'b1; + aw_en <= 1'b0; + end + else if (S_AXI_BREADY && axi_bvalid) + begin + aw_en <= 1'b1; + axi_awready <= 1'b0; + end + else + begin + axi_awready <= 1'b0; + end + end + end + + // Implement axi_awaddr latching + // This process is used to latch the address when both + // S_AXI_AWVALID and S_AXI_WVALID are valid. + + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + axi_awaddr <= 0; + end + else + begin + if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en) + begin + // Write Address latching + axi_awaddr <= S_AXI_AWADDR; + end + end + end + + // Implement axi_wready generation + // axi_wready is asserted for one S_AXI_ACLK clock cycle when both + // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + // de-asserted when reset is low. + + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + axi_wready <= 1'b0; + end + else + begin + if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en ) + begin + // slave is ready to accept write data when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_wready <= 1'b1; + end + else + begin + axi_wready <= 1'b0; + end + end + end + + // Implement memory mapped register select and write logic generation + // The write data is accepted and written to memory mapped registers when + // axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + // select byte enables of slave registers while writing. + // These registers are cleared when reset (active low) is applied. + // Slave register write enable is asserted when valid address and data are available + // and the slave is ready to accept the write address and write data. + assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID; + + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + slv_reg0 <= 32'd100; // power_thresh register, 16 bit LSB used, MSB used as general reset + slv_reg1 <= 32'd80; // power window register, 16 bit LSB used + slv_reg2 <= 32'd5000000; // num sample to skip register, 32 bit used + slv_reg3 <= 32'd100; // min plateau for short synq to be detected + slv_reg4 <= 0; + slv_reg5 <= 0; + slv_reg6 <= 0; + slv_reg7 <= 0; + slv_reg8 <= 0; + slv_reg9 <= 0; + slv_reg10 <= 0; + slv_reg11 <= 0; + slv_reg12 <= 0; + slv_reg13 <= 0; + slv_reg14 <= 0; + slv_reg15 <= 0; +// slv_reg16 <= 0; +// slv_reg17 <= 0; +// slv_reg18 <= 0; +// slv_reg19 <= 0; +// slv_reg20 <= 0; + slv_reg21 <= 0; + slv_reg22 <= 0; + slv_reg23 <= 0; + slv_reg24 <= 0; + slv_reg25 <= 0; + slv_reg26 <= 0; + slv_reg27 <= 0; + slv_reg28 <= 0; + slv_reg29 <= 0; + slv_reg30 <= 0; + slv_reg31 <= 0; + end + else begin + if (slv_reg_wren) + begin + case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 5'h00: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 0 + slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h01: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 1 + slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h02: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 2 + slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h03: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 3 + slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h04: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 4 + slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h05: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 5 + slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h06: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 6 + slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h07: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 7 + slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h08: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 8 + slv_reg8[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h09: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 9 + slv_reg9[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h0A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 10 + slv_reg10[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h0B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 11 + slv_reg11[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h0C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 12 + slv_reg12[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h0D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 13 + slv_reg13[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h0E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 14 + slv_reg14[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h0F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 15 + slv_reg15[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end +// 5'h10: +// for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) +// if ( S_AXI_WSTRB[byte_index] == 1 ) begin +// // Respective byte enables are asserted as per write strobes +// // Slave register 16 +// slv_reg16[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; +// end +// 5'h11: +// for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) +// if ( S_AXI_WSTRB[byte_index] == 1 ) begin +// // Respective byte enables are asserted as per write strobes +// // Slave register 17 +// slv_reg17[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; +// end +// 5'h12: +// for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) +// if ( S_AXI_WSTRB[byte_index] == 1 ) begin +// // Respective byte enables are asserted as per write strobes +// // Slave register 18 +// slv_reg18[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; +// end +// 5'h13: +// for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) +// if ( S_AXI_WSTRB[byte_index] == 1 ) begin +// // Respective byte enables are asserted as per write strobes +// // Slave register 19 +// slv_reg19[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; +// end +// 5'h14: +// for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) +// if ( S_AXI_WSTRB[byte_index] == 1 ) begin +// // Respective byte enables are asserted as per write strobes +// // Slave register 20 +// slv_reg20[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; +// end + 5'h15: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 21 + slv_reg21[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h16: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 22 + slv_reg22[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h17: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 23 + slv_reg23[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h18: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 24 + slv_reg24[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h19: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 25 + slv_reg25[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h1A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 26 + slv_reg26[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h1B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 27 + slv_reg27[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h1C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 28 + slv_reg28[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h1D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 29 + slv_reg29[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h1E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 30 + slv_reg30[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h1F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 31 + slv_reg31[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + default : begin + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; +// slv_reg16 <= slv_reg16; +// slv_reg17 <= slv_reg17; +// slv_reg18 <= slv_reg18; +// slv_reg19 <= slv_reg19; +// slv_reg20 <= slv_reg20; + slv_reg21 <= slv_reg21; + slv_reg22 <= slv_reg22; + slv_reg23 <= slv_reg23; + slv_reg24 <= slv_reg24; + slv_reg25 <= slv_reg25; + slv_reg26 <= slv_reg26; + slv_reg27 <= slv_reg27; + slv_reg28 <= slv_reg28; + slv_reg29 <= slv_reg29; + slv_reg30 <= slv_reg30; + slv_reg31 <= slv_reg31; + end + endcase + end + end + end + + // Implement write response logic generation + // The write response and response valid signals are asserted by the slave + // when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + // This marks the acceptance of address and indicates the status of + // write transaction. + + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + axi_bvalid <= 0; + axi_bresp <= 2'b0; + end + else + begin + if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID) + begin + // indicates a valid write response is available + axi_bvalid <= 1'b1; + axi_bresp <= 2'b0; // 'OKAY' response + end // work error responses in future + else + begin + if (S_AXI_BREADY && axi_bvalid) + //check if bready is asserted while bvalid is high) + //(there is a possibility that bready is always asserted high) + begin + axi_bvalid <= 1'b0; + end + end + end + end + + // Implement axi_arready generation + // axi_arready is asserted for one S_AXI_ACLK clock cycle when + // S_AXI_ARVALID is asserted. axi_awready is + // de-asserted when reset (active low) is asserted. + // The read address is also latched when S_AXI_ARVALID is + // asserted. axi_araddr is reset to zero on reset assertion. + + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + axi_arready <= 1'b0; + axi_araddr <= 32'b0; + end + else + begin + if (~axi_arready && S_AXI_ARVALID) + begin + // indicates that the slave has acceped the valid read address + axi_arready <= 1'b1; + // Read address latching + axi_araddr <= S_AXI_ARADDR; + end + else + begin + axi_arready <= 1'b0; + end + end + end + + // Implement axi_arvalid generation + // axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + // S_AXI_ARVALID and axi_arready are asserted. The slave registers + // data are available on the axi_rdata bus at this instance. The + // assertion of axi_rvalid marks the validity of read data on the + // bus and axi_rresp indicates the status of read transaction.axi_rvalid + // is deasserted on reset (active low). axi_rresp and axi_rdata are + // cleared to zero on reset (active low). + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + axi_rvalid <= 0; + axi_rresp <= 0; + end + else + begin + if (axi_arready && S_AXI_ARVALID && ~axi_rvalid) + begin + // Valid read data is available at the read data bus + axi_rvalid <= 1'b1; + axi_rresp <= 2'b0; // 'OKAY' response + end + else if (axi_rvalid && S_AXI_RREADY) + begin + // Read data is accepted by the master + axi_rvalid <= 1'b0; + end + end + end + + // Implement memory mapped register select and read logic generation + // Slave register read enable is asserted when valid address is available + // and the slave is ready to accept the read address. + assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid; + always @(*) + begin + // Address decoding for reading registers + case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 5'h00 : reg_data_out <= slv_reg0; + 5'h01 : reg_data_out <= slv_reg1; + 5'h02 : reg_data_out <= slv_reg2; + 5'h03 : reg_data_out <= slv_reg3; + 5'h04 : reg_data_out <= slv_reg4; + 5'h05 : reg_data_out <= slv_reg5; + 5'h06 : reg_data_out <= slv_reg6; + 5'h07 : reg_data_out <= slv_reg7; + 5'h08 : reg_data_out <= slv_reg8; + 5'h09 : reg_data_out <= slv_reg9; + 5'h0A : reg_data_out <= slv_reg10; + 5'h0B : reg_data_out <= slv_reg11; + 5'h0C : reg_data_out <= slv_reg12; + 5'h0D : reg_data_out <= slv_reg13; + 5'h0E : reg_data_out <= slv_reg14; + 5'h0F : reg_data_out <= slv_reg15; + 5'h10 : reg_data_out <= slv_reg16; + 5'h11 : reg_data_out <= slv_reg17; + 5'h12 : reg_data_out <= slv_reg18; + 5'h13 : reg_data_out <= slv_reg19; + 5'h14 : reg_data_out <= slv_reg20; + 5'h15 : reg_data_out <= slv_reg21; + 5'h16 : reg_data_out <= slv_reg22; + 5'h17 : reg_data_out <= slv_reg23; + 5'h18 : reg_data_out <= slv_reg24; + 5'h19 : reg_data_out <= slv_reg25; + 5'h1A : reg_data_out <= slv_reg26; + 5'h1B : reg_data_out <= slv_reg27; + 5'h1C : reg_data_out <= slv_reg28; + 5'h1D : reg_data_out <= slv_reg29; + 5'h1E : reg_data_out <= slv_reg30; + 5'h1F : reg_data_out <= slv_reg31; + default : reg_data_out <= 0; + endcase + end + + // Output register or memory read data + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + axi_rdata <= 0; + end + else + begin + // When there is a valid read address (S_AXI_ARVALID) with + // acceptance of read address by the slave (axi_arready), + // output the read dada + if (slv_reg_rden) + begin + axi_rdata <= reg_data_out; // register read data + end + end + end + + // Add user logic here + (* mark_debug = "true" *) reg num_sample_changed; + (* mark_debug = "true" *) wire [31:0] num_sample_delayed ; + (* mark_debug = "true" *) wire reset = ~S_AXI_ARESETN | slv_reg0[C_S_AXI_DATA_WIDTH-1]; + assign fifo_rst = reset ; + delayT #(.DATA_WIDTH(32), .DELAY(1)) num_sp_to_skip_delay_inst ( + .clock(S_AXI_ACLK), + .reset(reset), + .data_in(slv_reg2), + .data_out(num_sample_delayed) + ); + + // write process for status registers to read header information + always @( posedge S_AXI_ACLK ) + begin + if( reset ) begin + slv_reg16 <= 0; + slv_reg17 <= 0; + slv_reg18 <= 0; + slv_reg19 <= 0; + slv_reg20 <= 0; + end else begin + if (sig_valid) begin + slv_reg16 <= {29'b0, mcs_io} ; + slv_reg17 <= {20'b0, legacy_len} ; + end + if (ht_sig_valid) begin + slv_reg18 <= {25'b0, ht_mcs_io} ; + slv_reg19 <= {16'b0, ht_pkt_len_io} ; + end + if (fcs_valid) + slv_reg20 <= slv_reg20 + 1 ; + end + end + + always @( posedge S_AXI_ACLK ) + begin + if( S_AXI_ARESETN == 1'b0 ) + num_sample_changed <= 1'b0 ; + else + begin + if( num_sample_delayed == slv_reg2) + num_sample_changed <= 1'b0 ; + else + num_sample_changed <= 1'b1 ; + + end + end + (* mark_debug = "true" *) wire [31:0] phase_offset ; + (* mark_debug = "true" *) wire short_preamble_detected ; + (* mark_debug = "true" *) wire [3:0] state; + (* mark_debug = "true" *) wire [3:0] status_code; + (* mark_debug = "true" *) wire state_changed; + + (* mark_debug = "true" *) wire [31:0] sync_long_metric; + (* mark_debug = "true" *) wire sync_long_metric_stb; + (* mark_debug = "true" *) wire long_preamble_detected; + (* mark_debug = "true" *) wire [31:0] sync_long_out; + (* mark_debug = "true" *) wire sync_long_out_strobe; + (* mark_debug = "true" *) wire [2:0] sync_long_state; + + (* mark_debug = "true" *) wire pkt_begin; + (* mark_debug = "true" *) wire pkt_ht ; + (* mark_debug = "true" *) wire [7:0] pkt_rate ; + (* mark_debug = "true" *) wire [15:0] pkt_len ; + (* mark_debug = "true" *) wire [7:0] byte_out ; + (* mark_debug = "true" *) wire fcs_out_strobe; + (* mark_debug = "true" *) wire fcs_ok ; + (* mark_debug = "true" *) wire byte_out_strobe; + + (* mark_debug = "true" *) reg [3:0] rd_en_counter ; + + wire [3:0] legacy_rate; + wire [11:0] legacy_len; + wire legacy_sig_parity_ok; + wire legacy_sig_stb; + wire [2:0] mcs_sel = legacy_rate[2:0] ; + + wire ht_sig_stb; + wire ht_sig_crc_ok; + + // assign top level output to spy signal + assign ofdm_byte = byte_out ; + assign ofdm_byte_valid = byte_out_strobe ; + assign fcs_valid = fcs_ok & fcs_out_strobe ; + assign fcs_invalid = (~fcs_ok) & fcs_out_strobe; + assign pkt_len_io = legacy_len ; + assign sig_valid = legacy_sig_stb & legacy_sig_parity_ok; + assign sig_invalid = (~legacy_sig_parity_ok) & legacy_sig_stb; + + always @ (mcs_sel) + case (mcs_sel) + 3'b000: mcs_io = 6; + 3'b001: mcs_io = 4; + 3'b010: mcs_io = 2; + 3'b011: mcs_io = 0; + 3'b100: mcs_io = 7; + 3'b101: mcs_io = 5; + 3'b110: mcs_io = 3; + 3'b111: mcs_io = 1; + default: mcs_io = 0; + endcase + + assign ht_sig_valid = ht_sig_stb & ht_sig_crc_ok ; + assign ht_sig_invalid = ht_sig_stb & (~ht_sig_crc_ok) ; + + always @ (state or status_code) + begin + + if(state == 13) // ht sig error state + ht_unsupported = (status_code == E_UNSUPPORTED_MCS) || (status_code == E_UNSUPPORTED_CBW) || (status_code == E_UNSUPPORTED_STBC) || (status_code == E_UNSUPPORTED_FEC) || (status_code == E_UNSUPPORTED_SGI) || (status_code == E_UNSUPPORTED_SPATIAL); + else + ht_unsupported = 0; + + end + + // + + always @( posedge S_AXI_ACLK ) + begin + if( reset == 1'b1 ) + begin + rd_en_counter <= 4'b0 ; + rd_en <= 1'b0 ; + end + else + begin + if( enable == 1'b1 ) + begin + rd_en_counter = rd_en_counter + 1 ; + if(rd_en_counter == 4'd5) + begin + rd_en_counter = 4'b0 ; + if (~fifo_empty) + rd_en <= 1'b1; + else + rd_en <= 1'b0 ; + + end + else + rd_en <= 1'b0 ; + end + + end + end + + + dot11 dot11_inst ( + .clock(S_AXI_ACLK), + .enable(enable), + .reset(reset), + + .sample_in(sample_in), + .sample_in_strobe(sample_in_strobe), + + .power_thres(slv_reg0[15:0]), + .window_size(slv_reg1[15:0]), + .num_sample_to_skip(slv_reg2), + .num_sample_changed(num_sample_changed), + .min_plateau(slv_reg3), + // OUTPUT: bytes and FCS status + .pkt_begin(pkt_begin), + .pkt_ht(pkt_ht), + .pkt_rate(pkt_rate), + .pkt_len(pkt_len), + .byte_out_strobe(byte_out_strobe), + .byte_out(byte_out), + .data_out(data_out), + .data_out_valid(data_out_valid), + .fcs_out_strobe(fcs_out_strobe), + .fcs_ok(fcs_ok), + + // debug info + .state(state), + .status_code(status_code), + .state_changed(state_changed), + .power_trigger(trigger), + .short_preamble_detected(short_preamble_detected), + .phase_offset(phase_offset), + + .sync_long_metric(sync_long_metric), + .sync_long_metric_stb(sync_long_metric_stb), + .long_preamble_detected(long_preamble_detected), + .sync_long_out(sync_long_out), + .sync_long_out_strobe(sync_long_out_strobe), + .sync_long_state(sync_long_state), + + .legacy_rate(legacy_rate), + //.legacy_sig_rsvd(legacy_sig_rsvd), + .legacy_len(legacy_len), + //.legacy_sig_parity(legacy_sig_parity), + .legacy_sig_parity_ok(legacy_sig_parity_ok), + //.legacy_sig_tail(legacy_sig_tail), + .legacy_sig_stb(legacy_sig_stb), + //.sig_bits_spy(sig_bits_spy), + //.byte_count_spy(byte_count_spy), + + .ht_sig_stb(ht_sig_stb), + .ht_mcs(ht_mcs_io), + .ht_len(ht_pkt_len_io), + .ht_sig_crc_ok(ht_sig_crc_ok) + + + ); + // User logic ends + + endmodule diff --git a/verilog/intf_64bit.v b/verilog/intf_64bit.v new file mode 100644 index 0000000..fe4da46 --- /dev/null +++ b/verilog/intf_64bit.v @@ -0,0 +1,67 @@ +/******************************************************** + * An interface to assemble bytes into 64 bits. * + * * + * Author: Wei Liu * + ********************************************************/ +module intf_64bit ( + input clock, + input reset, + input enable, + input wire [15:0] pkt_len, + input wire [31:0] byte_index, + input wire [7:0] byte_in, + input wire byte_strobe, + + output reg [63:0] data_out, + output reg output_strobe +); + + + reg byte_strobe_delay ; + reg [63:0] dout ; + always @ (posedge clock) + begin + byte_strobe_delay <= byte_strobe ; + //data_out <= dout ; + end + + always @ (posedge clock) + begin + if(reset) begin + dout <= 64'h0 ; + data_out <= 64'h0; + output_strobe <= 1'b0 ; + end + else if(enable) begin + output_strobe <= 1'b0 ; + data_out <= dout ; + if(byte_strobe) begin + dout <= {byte_in, dout[63:8]} ; + end + if(byte_strobe_delay) begin + if(byte_index[2:0] == 3'b0 && byte_index[31:3] > 0 ) + output_strobe <= 1'b1 ; + else if (pkt_len == byte_index) begin + output_strobe <= 1'b1 ; + case (pkt_len[2:0]) + 3'b000: data_out <= dout; + 3'b001: begin data_out <= {56'b0,dout[63:56]}; dout <= {56'b0,dout[63:56]}; end + 3'b010: begin data_out <= {48'b0,dout[63:48]}; dout <= {48'b0,dout[63:48]}; end + 3'b011: begin data_out <= {40'b0,dout[63:40]}; dout <= {40'b0,dout[63:40]}; end + 3'b100: begin data_out <= {32'b0,dout[63:32]}; dout <= {32'b0,dout[63:32]}; end + 3'b101: begin data_out <= {24'b0,dout[63:24]}; dout <= {24'b0,dout[63:24]}; end + 3'b110: begin data_out <= {16'b0,dout[63:16]}; dout <= {16'b0,dout[63:16]}; end + 3'b111: begin data_out <= {8'b0,dout[63:8]}; dout <= {8'b0,dout[63:8]}; end + default: data_out <= dout; + + endcase + + end + + end + + end + + end + +endmodule diff --git a/verilog/ofdm_decoder.v b/verilog/ofdm_decoder.v index c4233df..5f9fa96 100644 --- a/verilog/ofdm_decoder.v +++ b/verilog/ofdm_decoder.v @@ -28,22 +28,24 @@ module ofdm_decoder output byte_out_strobe ); -reg conv_in_stb; -reg [2:0] conv_in0; -reg [2:0] conv_in1; -reg [1:0] conv_erase; +reg conv_in_stb, conv_in_stb_dly, do_descramble_dly; +reg [2:0] conv_in0, conv_in0_dly; +reg [2:0] conv_in1, conv_in1_dly; +reg [1:0] conv_erase, conv_erase_dly; wire [15:0] input_i = sample_in[31:16]; wire [15:0] input_q = sample_in[15:0]; -wire vit_ce = reset | (enable & conv_in_stb); +wire vit_ce = reset | (enable & conv_in_stb) | conv_in_stb_dly; + wire vit_clr = reset; +reg vit_clr_dly; wire vit_rdy; wire [1:0] erase; -assign conv_decoder_out_stb = vit_ce & vit_rdy; - +// assign conv_decoder_out_stb = vit_ce & vit_rdy; +assign conv_decoder_out_stb = m_axis_data_tvalid; // vit_rdy was used as data valid in the old version of the core, which is no longer the case reg [3:0] skip_bit; reg bit_in; reg bit_in_stb; @@ -78,15 +80,18 @@ deinterleave deinterleave_inst ( .erase(erase) ); +wire m_axis_data_tvalid ; + viterbi_v7_0 viterbi_inst ( - .clk(clock), - .ce(vit_ce), - .sclr(vit_clr), - .data_in0(conv_in0), - .data_in1(conv_in1), - .erase(conv_erase), - .rdy(vit_rdy), - .data_out(conv_decoder_out) + .aclk(clock), // input wire aclk + .aresetn(~vit_clr), // input wire aresetn + .aclken(vit_ce), // input wire aclken + .s_axis_data_tdata({5'b0,conv_in1_dly,5'b0,conv_in0_dly}), // input wire [15 : 0] s_axis_data_tdata + .s_axis_data_tuser({6'b0,conv_erase_dly}), // input wire [7 : 0] s_axis_data_tuser + .s_axis_data_tvalid(conv_in_stb_dly), // input wire s_axis_data_tvalid + .s_axis_data_tready(vit_rdy), // output wire s_axis_data_tready + .m_axis_data_tdata({idle_wire_7bit, conv_decoder_out}), // output wire [7 : 0] m_axis_data_tdata + .m_axis_data_tvalid(m_axis_data_tvalid) // output wire m_axis_data_tvalid ); @@ -153,7 +158,7 @@ always @(posedge clock) begin end if (deinter_out_count > 0) begin - if (~do_descramble) begin + if (~do_descramble_dly) begin bit_in <= conv_decoder_out; bit_in_stb <= conv_decoder_out_stb; end else begin @@ -173,4 +178,14 @@ always @(posedge clock) begin end end +// process used to delay things +// TODO: this is only a temp solution, as tready only rise one clock after ce goes high, delay statically by one clock, in future should take into account tready +always @(posedge clock) begin + conv_in1_dly <= conv_in1; + conv_in0_dly <= conv_in0; + conv_erase_dly <= conv_erase; + conv_in_stb_dly <= conv_in_stb ; + do_descramble_dly <= do_descramble; +end + endmodule diff --git a/verilog/power_trigger.v b/verilog/power_trigger.v index 3d6eaaa..c9a245a 100644 --- a/verilog/power_trigger.v +++ b/verilog/power_trigger.v @@ -4,13 +4,14 @@ module power_trigger input enable, input reset, - input set_stb, - input [7:0] set_addr, - input [31:0] set_data, - input [31:0] sample_in, input sample_in_strobe, + input [15:0] power_thres, + input [15:0] window_size, + input [31:0] num_sample_to_skip, + input num_sample_changed, + output [1:0] pw_state_spy, output reg trigger ); `include "common_params.v" @@ -18,34 +19,20 @@ module power_trigger localparam S_SKIP = 0; localparam S_IDLE = 1; localparam S_PACKET = 2; -reg [1:0] state; - -wire [15:0] power_thres; -wire [15:0] window_size; -wire [31:0] num_sample_to_skip; -wire num_sample_changed; +(* mark_debug = "true" *) reg [1:0] state; +(* mark_debug = "true" *) wire [15:0] power_thres; +(* mark_debug = "true" *) wire [15:0] window_size; +(* mark_debug = "true" *) wire [31:0] num_sample_to_skip; +(* mark_debug = "true" *) wire num_sample_changed; +(* mark_debug = "true" *) wire sample_in_strobe_dbg; +assign sample_in_strobe_dbg = sample_in_strobe ; reg [31:0] sample_count; -wire [15:0] input_i = sample_in[31:16]; +(* mark_debug = "true" *) wire [15:0] input_i = sample_in[31:16]; reg [15:0] abs_i; - -// threshold to claim a power trigger. -setting_reg #(.my_addr(SR_POWER_THRES), .width(16), .at_reset(100)) sr_0 ( - .clk(clock), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data), - .out(power_thres), .changed()); - -// power trigger window -setting_reg #(.my_addr(SR_POWER_WINDOW), .width(16), .at_reset(80)) sr_1 ( - .clk(clock), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data), - .out(window_size), .changed()); - -// num samples to skip initially -setting_reg #(.my_addr(SR_SKIP_SAMPLE), .width(32), .at_reset(5000000)) sr_2 ( - .clk(clock), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data), - .out(num_sample_to_skip), .changed(num_sample_changed)); - +assign pw_state_spy = state ; always @(posedge clock) begin if (reset) begin diff --git a/verilog/stage_mult.v b/verilog/stage_mult.v index f2cf626..4296866 100644 --- a/verilog/stage_mult.v +++ b/verilog/stage_mult.v @@ -38,44 +38,45 @@ wire signed [31:0] prod_2_q; wire signed [31:0] prod_3_i; wire signed [31:0] prod_3_q; -complex_multiplier mult_inst1 ( - .clk(clock), - .ar(X0), - .ai(X1), - .br(Y0), - .bi(Y1), - .pr(prod_0_i), - .pi(prod_0_q) +complex_multiplier mult_inst ( + .aclk(clock), + .s_axis_a_tvalid(input_strobe), + .s_axis_a_tdata({X1,X0}), + .s_axis_b_tvalid(input_strobe), + .s_axis_b_tdata({Y1,Y0}), + .m_axis_dout_tvalid(), + .m_axis_dout_tdata({prod_0_q,prod_0_i}) ); complex_multiplier mult_inst2 ( - .clk(clock), - .ar(X2), - .ai(X3), - .br(Y2), - .bi(Y3), - .pr(prod_1_i), - .pi(prod_1_q) + .aclk(clock), + .s_axis_a_tvalid(input_strobe), + .s_axis_a_tdata({X3,X2}), + .s_axis_b_tvalid(input_strobe), + .s_axis_b_tdata({Y3,Y2}), + .m_axis_dout_tvalid(), + .m_axis_dout_tdata({prod_1_q,prod_1_i}) ); complex_multiplier mult_inst3 ( - .clk(clock), - .ar(X4), - .ai(X5), - .br(Y4), - .bi(Y5), - .pr(prod_2_i), - .pi(prod_2_q) + .aclk(clock), + .s_axis_a_tvalid(input_strobe), + .s_axis_a_tdata({X5,X4}), + .s_axis_b_tvalid(input_strobe), + .s_axis_b_tdata({Y5,Y4}), + .m_axis_dout_tvalid(), + .m_axis_dout_tdata({prod_2_q,prod_2_i}) ); + complex_multiplier mult_inst4 ( - .clk(clock), - .ar(X6), - .ai(X7), - .br(Y6), - .bi(Y7), - .pr(prod_3_i), - .pi(prod_3_q) + .aclk(clock), + .s_axis_a_tvalid(input_strobe), + .s_axis_a_tdata({X7,X6}), + .s_axis_b_tvalid(input_strobe), + .s_axis_b_tdata({Y7,Y6}), + .m_axis_dout_tvalid(), + .m_axis_dout_tdata({prod_3_q,prod_3_i}) ); reg signed [31:0] sum_i1; diff --git a/verilog/sync_long.v b/verilog/sync_long.v index fb9054a..2387f65 100644 --- a/verilog/sync_long.v +++ b/verilog/sync_long.v @@ -3,10 +3,6 @@ module sync_long ( input reset, input enable, - input set_stb, - input [7:0] set_addr, - input [31:0] set_data, - input [31:0] sample_in, input sample_in_strobe, input signed [31:0] phase_offset, @@ -30,13 +26,13 @@ localparam IN_BUF_LEN_SHIFT = 8; localparam NUM_STS_TAIL = 32; -reg [15:0] in_offset; -reg [IN_BUF_LEN_SHIFT-1:0] in_waddr; -reg [IN_BUF_LEN_SHIFT-1:0] in_raddr; -wire [IN_BUF_LEN_SHIFT-1:0] gi_skip = short_gi? 9: 17; -reg signed [31:0] num_input_produced; -reg signed [31:0] num_input_consumed; -reg signed [31:0] num_input_avail; +(* mark_debug = "true" *) reg [15:0] in_offset; +(* mark_debug = "true" *) reg [IN_BUF_LEN_SHIFT-1:0] in_waddr; +(* mark_debug = "true" *) reg [IN_BUF_LEN_SHIFT-1:0] in_raddr; +(* mark_debug = "true" *) wire [IN_BUF_LEN_SHIFT-1:0] gi_skip = short_gi? 9: 17; +(* mark_debug = "true" *) reg signed [31:0] num_input_produced; +(* mark_debug = "true" *) reg signed [31:0] num_input_consumed; +(* mark_debug = "true" *) reg signed [31:0] num_input_avail; reg [2:0] mult_stage; reg [1:0] sum_stage; @@ -54,6 +50,13 @@ reg sum_stb; reg signed [31:0] phase_correction; reg signed [31:0] next_phase_correction; +reg reset_delay ; // add reset signal for fft, somehow all kinds of event flag raises when feeding real rf signal, maybe reset will help +(* mark_debug = "true" *) wire fft_resetn ; + +always @(posedge clock) begin + reset_delay = reset ; +end +assign fft_resetn = (~reset) & (~reset_delay); // make sure resetn is at least 2 clock cycles low complex_to_mag #(.DATA_WIDTH(32)) sum_mag_inst ( .clock(clock), @@ -72,7 +75,7 @@ reg [31:0] metric_max1; reg [(IN_BUF_LEN_SHIFT-1):0] addr1; reg [31:0] metric_max2; reg [(IN_BUF_LEN_SHIFT-1):0] addr2; -reg [15:0] gap; +(* mark_debug = "true" *) reg [15:0] gap; reg [31:0] cross_corr_buf[0:15]; @@ -121,25 +124,27 @@ localparam S_WAIT_FOR_SECOND_PEAK = 2; localparam S_IDLE = 3; localparam S_FFT = 4; -reg fft_start; -wire fft_start_delayed; -wire fft_in_stb; -reg fft_loading; -wire signed [15:0] fft_in_re; -wire signed [15:0] fft_in_im; -wire [22:0] fft_out_re; -wire [22:0] fft_out_im; -wire fft_ready; -wire fft_done; -wire fft_busy; -wire fft_valid; +(* mark_debug = "true" *) reg fft_start; +(* mark_debug = "true" *) wire fft_in_stb; +(* mark_debug = "true" *) reg fft_loading; +(* mark_debug = "true" *) wire signed [15:0] fft_in_re; +(* mark_debug = "true" *) wire signed [15:0] fft_in_im; +(* mark_debug = "true" *) wire [22:0] fft_out_re; +(* mark_debug = "true" *) wire [22:0] fft_out_im; +(* mark_debug = "true" *) wire fft_ready; +(* mark_debug = "true" *) wire fft_done; +(* mark_debug = "true" *) wire fft_busy; +(* mark_debug = "true" *) wire fft_valid; wire [31:0] fft_out = {fft_out_re[22:7], fft_out_im[22:7]}; -wire signed [15:0] raw_i; -wire signed [15:0] raw_q; -reg raw_stb; - +(* mark_debug = "true" *) wire signed [15:0] raw_i; +(* mark_debug = "true" *) wire signed [15:0] raw_q; +(* mark_debug = "true" *) reg raw_stb; +wire idle_line1, idle_line2 ; +(* mark_debug = "true" *) wire fft_din_data_tlast_delayed ; +(* mark_debug = "true" *) reg fft_din_data_tlast ; +(* mark_debug = "true" *) wire m_axis_data_tlast, s_axis_config_tready, event_frame_started, event_tlast_unexpected, event_tlast_missing, event_status_channel_halt, event_data_in_channel_halt, event_data_out_channel_halt; ram_2port #(.DWIDTH(32), .AWIDTH(IN_BUF_LEN_SHIFT)) in_buf ( .clka(clock), .ena(1), @@ -173,29 +178,35 @@ rotate rotate_inst ( .output_strobe(fft_in_stb) ); -delayT #(.DATA_WIDTH(1), .DELAY(9)) fft_delay_inst ( +delayT #(.DATA_WIDTH(1), .DELAY(10)) fft_delay_inst ( .clock(clock), .reset(reset), - .data_in(fft_start), - .data_out(fft_start_delayed) + .data_in(fft_din_data_tlast), + .data_out(fft_din_data_tlast_delayed) ); -xfft_v7_1 dft_inst ( - .clk(clock), - .fwd_inv(1), - .start(fft_start_delayed), - .fwd_inv_we(1), - - .xn_re(fft_in_re), - .xn_im(fft_in_im), - .xk_re(fft_out_re), - .xk_im(fft_out_im), - .rfd(fft_ready), - .done(fft_done), - .busy(fft_busy), - .dv(fft_valid) +xfft_v9 dft_inst ( + .aclk(clock), + .aresetn(fft_resetn), + .s_axis_config_tdata({7'b0, 1'b1}), // input wire [7 : 0] s_axis_config_tdata, use LSB to indicate it is forward transform, the rest should be ignored + .s_axis_config_tvalid(1'b1), // input wire s_axis_config_tvalid + .s_axis_config_tready(s_axis_config_tready), // output wire s_axis_config_tready + .s_axis_data_tdata({fft_in_im, fft_in_re}), // input wire [31 : 0] s_axis_data_tdata + .s_axis_data_tvalid(fft_in_stb), // input wire s_axis_data_tvalid + .s_axis_data_tready(fft_ready), // output wire s_axis_data_tready + .s_axis_data_tlast(fft_din_data_tlast_delayed), // input wire s_axis_data_tlast + .m_axis_data_tdata({idle_line1,fft_out_im, idle_line2, fft_out_re}), // output wire [47 : 0] m_axis_data_tdata + .m_axis_data_tvalid(fft_valid), // output wire m_axis_data_tvalid + .m_axis_data_tready(1'b1), // input wire m_axis_data_tready + .m_axis_data_tlast(m_axis_data_tlast), // output wire m_axis_data_tlast + .event_frame_started(event_frame_started), // output wire event_frame_started + .event_tlast_unexpected(event_tlast_unexpected), // output wire event_tlast_unexpected + .event_tlast_missing(event_tlast_missing), // output wire event_tlast_missing + .event_status_channel_halt(event_status_channel_halt), // output wire event_status_channel_halt + .event_data_in_channel_halt(event_data_in_channel_halt), // output wire event_data_in_channel_halt + .event_data_out_channel_halt(event_data_out_channel_halt) // output wire event_data_out_channel_halt ); reg [15:0] num_sample; @@ -210,6 +221,7 @@ always @(posedge clock) begin end do_clear(); state <= S_SKIPPING; + fft_din_data_tlast <= 1'b0; end else if (enable) begin if (sample_in_strobe && state != S_SKIPPING) begin in_waddr <= in_waddr + 1; @@ -323,8 +335,13 @@ always @(posedge clock) begin if (fft_start | fft_loading) begin in_offset <= in_offset + 1; + + if( in_offset == 62) begin + fft_din_data_tlast <= 1'b1; + end if (in_offset == 63) begin + fft_din_data_tlast <= 1'b0; fft_loading <= 0; num_ofdm_symbol <= num_ofdm_symbol + 1; if (num_ofdm_symbol > 0) begin diff --git a/verilog/sync_short.v b/verilog/sync_short.v index 9c9ef30..42fea66 100644 --- a/verilog/sync_short.v +++ b/verilog/sync_short.v @@ -5,9 +5,7 @@ module sync_short ( input reset, input enable, - input set_stb, - input [7:0] set_addr, - input [31:0] set_data, + input [31:0] min_plateau, input [31:0] sample_in, input sample_in_strobe, @@ -33,7 +31,7 @@ wire mag_sq_stb; wire [31:0] mag_sq_avg; wire mag_sq_avg_stb; -reg [31:0] prod_thres; +(* mark_debug = "true" *) reg [31:0] prod_thres; wire [31:0] sample_delayed; wire sample_delayed_stb; @@ -56,28 +54,20 @@ wire freq_offset_stb; reg [31:0] phase_out_neg; -wire [31:0] delay_prod_avg_mag; -wire delay_prod_avg_mag_stb; +(* mark_debug = "true" *) wire [31:0] delay_prod_avg_mag; +(* mark_debug = "true" *) wire delay_prod_avg_mag_stb; -reg [31:0] plateau_count; +(* mark_debug = "true" *) reg [31:0] plateau_count; // this is to ensure that the short preambles contains both positive and // negative in-phase, to avoid raise false positives when there is a constant // power reg [31:0] pos_count; reg [31:0] min_pos; -reg has_pos; +(* mark_debug = "true" *) reg has_pos; reg [31:0] neg_count; reg [31:0] min_neg; -reg has_neg; - -wire [31:0] min_plateau; - -// minimal number of samples that has to exceed plateau threshold to claim -// a short preamble -setting_reg #(.my_addr(SR_MIN_PLATEAU), .width(32), .at_reset(100)) sr_0 ( - .clk(clock), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data), - .out(min_plateau), .changed()); +(* mark_debug = "true" *) reg has_neg; complex_to_mag_sq mag_sq_inst (