diff --git a/verilog/openofdm_rx.v b/verilog/openofdm_rx.v
index 1559d61..968a6ef 100644
--- a/verilog/openofdm_rx.v
+++ b/verilog/openofdm_rx.v
@@ -115,6 +115,7 @@
 
 	assign slv_reg31 = `OPENOFDM_RX_GIT_REV;
 
+	wire power_trigger;
 	wire sig_valid = (pkt_header_valid_strobe&pkt_header_valid);
 	wire receiver_rst;
 
@@ -127,6 +128,8 @@
 		.q_data(sample_in[15:0]),
 		.iq_valid(sample_in_strobe),
 
+		.power_trigger(power_trigger),
+
 		.signal_len(pkt_len),
     	.sig_valid(sig_valid),
 
@@ -186,7 +189,7 @@
 		.state_changed(state_changed),
 		.state_history(slv_reg20),
 		// power trigger
-		.power_trigger(),
+		.power_trigger(power_trigger),
 
 		// sync short
 		.short_preamble_detected(short_preamble_detected),
diff --git a/verilog/signal_watchdog.v b/verilog/signal_watchdog.v
index 4c7baa5..7239ef1 100644
--- a/verilog/signal_watchdog.v
+++ b/verilog/signal_watchdog.v
@@ -14,6 +14,8 @@ module signal_watchdog
     input signed [(IQ_DATA_WIDTH-1):0] q_data,
     input iq_valid,
 
+    input power_trigger,
+
     input [15:0] signal_len,
     input sig_valid,
 
@@ -45,7 +47,7 @@ module signal_watchdog
 
     assign receiver_rst_pulse = (receiver_rst_internal&&(~receiver_rst_reg));
 
-    assign receiver_rst = ( receiver_rst_reg | (sig_valid && (signal_len<min_signal_len_th || signal_len>max_signal_len_th)) );
+    assign receiver_rst = ( power_trigger & ( receiver_rst_reg | (sig_valid && (signal_len<min_signal_len_th || signal_len>max_signal_len_th)) ) );
 
     always @(posedge clk) begin
         if (~rstn) begin