ExternalVendorCode/openofdm
1
0
Fork 0
mirror of https://github.com/jhshi/openofdm.git synced 2025-01-02 03:57:09 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

fix dot11 port pinout

Browse Source
This commit is contained in:
Jinghao Shi 2017-04-21 13:42:09 -04:00
parent b7361b2feb
commit 079744bec1
1 changed files with 16 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
verilog/dot11_tb.v
View File

@ -37,12 +37,12 @@ wire conv_decoder_out_stb;
wire descramble_out; wire descramble_out;
wire descramble_out_strobe; wire descramble_out_strobe;
wire [3:0] data_rate; wire [3:0] legacy_rate;
wire signal_reserved; wire legacy_sig_rsvd;
wire [11:0] length; wire [11:0] legacy_len;
wire parity; wire legacy_sig_parity;
wire [5:0] signal_tail; wire [5:0] legacy_sig_tail;
wire signal_out_strobe; wire legacy_sig_stb;
reg signal_done; reg signal_done;
wire [3:0] dot11_state; wire [3:0] dot11_state;
@ -88,7 +88,7 @@ integer byte_out_fd;
`endif `endif
initial begin initial begin
$dumpfile("dot11_decoder.vcd"); $dumpfile("dot11.vcd");
$dumpvars; $dumpvars;
$display("Reading memory from..."); $display("Reading memory from...");
@ -155,7 +155,7 @@ always @(posedge clock) begin
clk_count <= clk_count + 1; clk_count <= clk_count + 1;
end end
if (signal_out_strobe) begin if (legacy_sig_stb) begin
end end
if (sample_in_strobe && power_trigger) begin if (sample_in_strobe && power_trigger) begin
@ -196,9 +196,9 @@ always @(posedge clock) begin
$fflush(equalizer_out_fd); $fflush(equalizer_out_fd);
end end
if (signal_out_strobe) begin if (legacy_sig_stb) begin
signal_done <= 1; signal_done <= 1;
$fwrite(signal_fd, "%04b %b %012b %b %06b", data_rate, signal_reserved, length, parity, signal_tail); $fwrite(signal_fd, "%04b %b %012b %b %06b", legacy_rate, legacy_sig_rsvd, legacy_len, legacy_sig_parity, legacy_sig_tail);
$fflush(signal_fd); $fflush(signal_fd);
end end
@ -272,12 +272,12 @@ dot11 dot11_inst (
.byte_out(byte_out), .byte_out(byte_out),
.byte_out_strobe(byte_out_strobe), .byte_out_strobe(byte_out_strobe),
.data_rate(data_rate), .legacy_rate(legacy_rate),
.signal_reserved(signal_reserved), .legacy_sig_rsvd(legacy_sig_rsvd),
.length(length), .legacy_len(legacy_len),
.parity(parity), .legacy_sig_parity(legacy_sig_parity),
.signal_tail(signal_tail), .legacy_sig_tail(legacy_sig_tail),
.signal_out_strobe(signal_out_strobe) .legacy_sig_stb(legacy_sig_stb)
); );
endmodule endmodule