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58 lines
2.6 KiB
ReStructuredText
58 lines
2.6 KiB
ReStructuredText
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Integration with USRP
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=====================
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|project| was originally developed on Ettus Research USRP N210 platform. This
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short guide explains how to modify the USRP N210's FPGA code base to
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accommodate |project|.
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USRP N2x0 FPGA Overview
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-----------------------
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The top level model of USRP N2x0 (N200 and N210) can be found in
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:file:`top/N2x0/u2plus.v`. It instantiates the ``u2plus_core`` module, which
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contains the core modules such as the receiver and transmit chain. In
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particular, the receive chain includes ``rx_frontend``, ``ddc_chain`` and
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``vita_rx_chain``. Similarly, the transmit chain includes ``vita_tx_chain``,
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``duc_chain`` and ``tx_frontend``.
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The code base contains placeholder modules (``dsp_rx_glue`` and ``dsp_tx_glue``)
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for extension. These modules are controlled by Verilog compilation flags and by
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default they are simply pass-through and have no effect on the signal processing
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at all.
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Enable Custom Modules
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---------------------
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Take the receive chain as an example, inside ``dsp_rx_glue`` module, it checks
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the ``RX_DSP0_MODULE`` macro and instantiates it if found. The macro can be
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defined in a customized Makefile. Make a copy of the
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:file:`top/N2x0/Makefile.N210R4`, name it to
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:file:`top/N2x0/Makefile.N210R4.custom`. And then make these changes.
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- Change ``BUILD_DIR`` to ``$(abspath build$(ISE)-N210R4-custom)``. This will
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create a new build directory for our custom build.
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- Comment out ``CUSTOM_SRCS`` and ``CUSTOM_DEFS``. We will define them in a
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separate Makefile.
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- Find ``Verilog Macros`` and change it to
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``"LVDS=1|RX_DSP0_MODULE=custom_dsp_rx|RX_DSP1_MODULE=custom_dsp_rx|TX_DSP0_MODULE=custom_dsp_tx|TX_DSP1_MODULE=custom_dsp_tx|FIFO_CTRL_NO_TIME=1"``.
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This defines the macros to so that the custom modules are instantiated by the
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glue modules mentioned earlier.
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After these changes, the two modules in :file:`custom/custom_dsp_rx.v` and
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:file:`custom/custom_dsp_tx.v` will be instantiated. By default they are simply
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pass-through. For instance, the output of RF frontend are directly connnected to
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the input of DDC, and the output of DDC are directly connected to the VITA RX
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module.
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To integrate |project|, we only need to *insert* it after the DDC but before
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VITA RX module. That is, the ``sample_in/sample_in_strobe`` of the ``dot11``
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module should be connected to the ``ddc_out/ddc_out_strobe`` signal.
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Also note that two receive chains are defined in ``u2plus_core`` module, so that
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the two antenna ports can be configured in TX/RX or RX/RX mode. To save FPGA
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resource, you may want to comment out one of the RX chains to make more room for
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|project|.
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