2017-04-03 16:52:03 +00:00
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`include "common_defs.v"
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module dot11 (
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input clock,
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input enable,
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input reset,
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2017-04-03 18:31:25 +00:00
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// setting registers
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2019-12-10 13:09:31 +00:00
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//input set_stb,
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//input [7:0] set_addr,
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//input [31:0] set_data,
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// add ports for register based inputs
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2019-12-10 12:31:16 +00:00
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input [10:0] power_thres,
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2019-12-10 13:09:31 +00:00
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input [31:0] min_plateau,
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2017-04-03 16:52:03 +00:00
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2019-12-10 12:31:16 +00:00
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// INPUT: RSSI
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input [10:0] rssi_half_db,
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2017-04-03 16:52:03 +00:00
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// INPUT: I/Q sample
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2020-06-12 08:24:59 +00:00
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input [31:0] sample_in,
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input sample_in_strobe,
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input soft_decoding,
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2017-04-03 16:52:03 +00:00
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// OUTPUT: bytes and FCS status
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2020-06-12 08:24:59 +00:00
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output reg demod_is_ongoing,
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output reg pkt_begin,
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output reg pkt_ht,
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output reg pkt_header_valid,
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output reg pkt_header_valid_strobe,
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output reg ht_unsupport,
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output reg [7:0] pkt_rate,
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output reg [15:0] pkt_len,
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output reg [15:0] pkt_len_total,
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output byte_out_strobe,
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output [7:0] byte_out,
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output reg [15:0] byte_count_total,
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output reg [15:0] byte_count,
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output reg fcs_out_strobe,
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output reg fcs_ok,
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2017-04-03 16:52:03 +00:00
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/////////////////////////////////////////////////////////
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// DEBUG PORTS
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/////////////////////////////////////////////////////////
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// decode status
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2020-06-12 08:24:59 +00:00
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output reg [3:0] state,
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output reg [3:0] status_code,
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2017-04-03 16:52:03 +00:00
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output state_changed,
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// power trigger
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output power_trigger,
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// sync short
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output short_preamble_detected,
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output [31:0] phase_offset,
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// sync long
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output [31:0] sync_long_metric,
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output sync_long_metric_stb,
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output long_preamble_detected,
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output [31:0] sync_long_out,
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output sync_long_out_strobe,
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output [2:0] sync_long_state,
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// equalizer
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output [31:0] equalizer_out,
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output equalizer_out_strobe,
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output [2:0] equalizer_state,
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2017-04-21 17:41:49 +00:00
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// legacy signal info
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output reg legacy_sig_stb,
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output [3:0] legacy_rate,
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output legacy_sig_rsvd,
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output [11:0] legacy_len,
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output legacy_sig_parity,
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output legacy_sig_parity_ok,
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output [5:0] legacy_sig_tail,
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2017-04-03 16:52:03 +00:00
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// ht signal info
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2017-04-21 17:41:49 +00:00
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output reg ht_sig_stb,
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output [6:0] ht_mcs,
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output ht_cbw,
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2017-04-03 16:52:03 +00:00
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output [15:0] ht_len,
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2017-04-21 17:41:49 +00:00
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output ht_smoothing,
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output ht_not_sounding,
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output ht_aggregation,
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output [1:0] ht_stbc,
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output ht_fec_coding,
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2017-04-03 16:52:03 +00:00
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output ht_sgi,
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2017-04-21 17:41:49 +00:00
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output [1:0] ht_num_ext,
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2017-04-03 16:52:03 +00:00
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output reg ht_sig_crc_ok,
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2017-04-21 17:41:49 +00:00
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// decoding pipeline
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2017-04-03 16:52:03 +00:00
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output [5:0] demod_out,
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output demod_out_strobe,
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2019-12-10 12:45:43 +00:00
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output [7:0] deinterleave_erase_out,
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2019-12-10 12:31:16 +00:00
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output deinterleave_erase_out_strobe,
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2017-04-03 16:52:03 +00:00
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output conv_decoder_out,
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output conv_decoder_out_stb,
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output descramble_out,
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output descramble_out_strobe
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);
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`include "common_params.v"
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////////////////////////////////////////////////////////////////////////////////
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// Shared rotation LUT for sync_long and equalizer
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////////////////////////////////////////////////////////////////////////////////
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wire [`ROTATE_LUT_LEN_SHIFT-1:0] sync_long_rot_addr;
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wire [31:0] sync_long_rot_data;
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wire [`ROTATE_LUT_LEN_SHIFT-1:0] eq_rot_addr;
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wire [31:0] eq_rot_data;
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rot_lut rot_lut_inst (
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.clka(clock),
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.addra(sync_long_rot_addr),
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.douta(sync_long_rot_data),
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.clkb(clock),
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.addrb(eq_rot_addr),
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.doutb(eq_rot_data)
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);
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// Shared phase module for sync_short and equalizer
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////////////////////////////////////////////////////////////////////////////////
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wire [31:0] sync_short_phase_in_i;
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wire [31:0] sync_short_phase_in_q;
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wire sync_short_phase_in_stb;
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wire [31:0] sync_short_phase_out;
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wire sync_short_phase_out_stb;
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wire [31:0] eq_phase_in_i;
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wire [31:0] eq_phase_in_q;
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wire eq_phase_in_stb;
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wire [31:0] eq_phase_out;
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wire eq_phase_out_stb;
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wire[31:0] phase_in_i = state == S_SYNC_SHORT?
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sync_short_phase_in_i: eq_phase_in_i;
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wire[31:0] phase_in_q = state == S_SYNC_SHORT?
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sync_short_phase_in_q: eq_phase_in_q;
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wire phase_in_stb = state == S_SYNC_SHORT?
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sync_short_phase_in_stb: eq_phase_in_stb;
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wire [31:0] phase_out;
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wire phase_out_stb;
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assign sync_short_phase_out = phase_out;
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assign sync_short_phase_out_stb = phase_out_stb;
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assign eq_phase_out = phase_out;
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assign eq_phase_out_stb = phase_out_stb;
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phase phase_inst (
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.clock(clock),
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.reset(reset),
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.enable(enable),
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.in_i(phase_in_i),
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.in_q(phase_in_q),
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.input_strobe(phase_in_stb),
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.phase(phase_out),
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.output_strobe(phase_out_stb)
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);
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////////////////////////////////////////////////////////////////////////////////
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2019-12-10 12:31:16 +00:00
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reg sync_short_reset;
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reg sync_long_reset;
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wire sync_short_enable = state == S_SYNC_SHORT;
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reg sync_long_enable;
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2017-04-03 16:52:03 +00:00
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reg equalizer_reset;
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reg equalizer_enable;
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reg ht_next;
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wire eq_out_stb_delayed;
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wire [15:0] eq_out_i = equalizer_out[31:16];
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wire [15:0] eq_out_q = equalizer_out[15:0];
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wire [15:0] eq_out_i_delayed;
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wire [15:0] eq_out_q_delayed;
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reg [15:0] abs_eq_i;
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reg [15:0] abs_eq_q;
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reg [3:0] rot_eq_count;
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reg [3:0] normal_eq_count;
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// OFDM control
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reg ofdm_reset;
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reg ofdm_enable;
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reg ofdm_in_stb;
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reg [15:0] ofdm_in_i;
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reg [15:0] ofdm_in_q;
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reg do_descramble;
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reg [31:0] num_bits_to_decode;
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reg short_gi;
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2020-06-12 08:24:59 +00:00
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reg [3:0] old_state;
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2019-12-10 12:31:16 +00:00
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assign power_trigger = (rssi_half_db>=power_thres? 1: 0);
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2017-04-03 16:52:03 +00:00
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assign state_changed = state != old_state;
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// SIGNAL information
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2020-06-12 08:24:59 +00:00
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reg [23:0] signal_bits;
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2017-04-03 16:52:03 +00:00
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2017-04-21 17:41:49 +00:00
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assign legacy_rate = signal_bits[3:0];
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assign legacy_sig_rsvd = signal_bits[4];
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assign legacy_len = signal_bits[16:5];
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assign legacy_sig_parity = signal_bits[17];
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assign legacy_sig_tail = signal_bits[23:18];
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assign legacy_sig_parity_ok = ~^signal_bits[17:0];
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2017-04-03 16:52:03 +00:00
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// HT-SIG information
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2020-06-12 08:24:59 +00:00
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reg [23:0] ht_sig1;
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reg [23:0] ht_sig2;
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2017-04-03 16:52:03 +00:00
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2017-04-21 17:41:49 +00:00
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assign ht_mcs = ht_sig1[6:0];
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assign ht_cbw = ht_sig1[7];
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2017-04-03 16:52:03 +00:00
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assign ht_len = ht_sig1[23:8];
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2017-04-21 17:41:49 +00:00
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assign ht_smoothing = ht_sig2[0];
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assign ht_not_sounding = ht_sig2[1];
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assign ht_aggregation = ht_sig2[3];
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assign ht_stbc = ht_sig2[5:4];
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assign ht_fec_coding = ht_sig2[6];
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2017-04-03 16:52:03 +00:00
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assign ht_sgi = ht_sig2[7];
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2017-04-21 17:41:49 +00:00
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assign ht_num_ext = ht_sig2[9:8];
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2017-04-03 16:52:03 +00:00
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wire ht_rsvd = ht_sig2[2];
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wire [7:0] crc = ht_sig2[17:10];
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wire [5:0] ht_sig_tail = ht_sig2[23:18];
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reg crc_in_stb;
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reg crc_in;
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reg [7:0] crc_count;
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reg crc_reset;
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wire [7:0] crc_out;
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reg [31:0] sample_count;
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wire fcs_enable = state == S_DECODE_DATA && byte_out_strobe;
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wire fcs_reset = state_changed && state == S_DECODE_DATA;
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wire [7:0] byte_reversed;
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wire [31:0] pkt_fcs;
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assign byte_reversed[0] = byte_out[7];
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assign byte_reversed[1] = byte_out[6];
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assign byte_reversed[2] = byte_out[5];
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assign byte_reversed[3] = byte_out[4];
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assign byte_reversed[4] = byte_out[3];
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assign byte_reversed[5] = byte_out[2];
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assign byte_reversed[6] = byte_out[1];
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assign byte_reversed[7] = byte_out[0];
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reg [15:0] sync_long_out_count;
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2019-12-10 12:31:16 +00:00
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/*
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2017-04-03 16:52:03 +00:00
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power_trigger power_trigger_inst (
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.clock(clock),
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.enable(enable),
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.reset(reset),
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.sample_in(sample_in),
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.sample_in_strobe(sample_in_strobe),
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2019-12-10 13:09:31 +00:00
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.power_thres(power_thres),
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.window_size(window_size),
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.num_sample_to_skip(num_sample_to_skip),
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.num_sample_changed(num_sample_changed),
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2017-04-03 16:52:03 +00:00
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2019-12-10 13:09:31 +00:00
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.pw_state_spy(pw_state_spy),
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2017-04-03 16:52:03 +00:00
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.trigger(power_trigger)
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);
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2019-12-10 12:31:16 +00:00
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*/
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2017-04-03 16:52:03 +00:00
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sync_short sync_short_inst (
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.clock(clock),
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.reset(reset | sync_short_reset),
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.enable(enable & sync_short_enable),
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2019-12-10 13:09:31 +00:00
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.min_plateau(min_plateau),
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2017-04-03 16:52:03 +00:00
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.sample_in(sample_in),
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.sample_in_strobe(sample_in_strobe),
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.phase_in_i(sync_short_phase_in_i),
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.phase_in_q(sync_short_phase_in_q),
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.phase_in_stb(sync_short_phase_in_stb),
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.phase_out(sync_short_phase_out),
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.phase_out_stb(sync_short_phase_out_stb),
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.short_preamble_detected(short_preamble_detected),
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.phase_offset(phase_offset)
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);
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sync_long sync_long_inst (
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.clock(clock),
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.reset(reset | sync_long_reset),
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.enable(enable & sync_long_enable),
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.sample_in(sample_in),
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.sample_in_strobe(sample_in_strobe),
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.phase_offset(phase_offset),
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.short_gi(short_gi),
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.rot_addr(sync_long_rot_addr),
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.rot_data(sync_long_rot_data),
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.metric(sync_long_metric),
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.metric_stb(sync_long_metric_stb),
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.long_preamble_detected(long_preamble_detected),
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.state(sync_long_state),
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.sample_out(sync_long_out),
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.sample_out_strobe(sync_long_out_strobe)
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);
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equalizer equalizer_inst (
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.clock(clock),
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.reset(reset | equalizer_reset),
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.enable(enable & equalizer_enable),
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|
|
.sample_in(sync_long_out),
|
|
|
|
.sample_in_strobe(sync_long_out_strobe),
|
|
|
|
.ht_next(ht_next),
|
|
|
|
|
|
|
|
.phase_in_i(eq_phase_in_i),
|
|
|
|
.phase_in_q(eq_phase_in_q),
|
|
|
|
.phase_in_stb(eq_phase_in_stb),
|
|
|
|
|
|
|
|
.phase_out(eq_phase_out),
|
|
|
|
.phase_out_stb(eq_phase_out_stb),
|
|
|
|
|
|
|
|
.rot_addr(eq_rot_addr),
|
|
|
|
.rot_data(eq_rot_data),
|
|
|
|
|
|
|
|
.sample_out(equalizer_out),
|
|
|
|
.sample_out_strobe(equalizer_out_strobe),
|
|
|
|
|
|
|
|
.state(equalizer_state)
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
|
|
delayT #(.DATA_WIDTH(33), .DELAY(6)) eq_delay_inst (
|
|
|
|
.clock(clock),
|
|
|
|
.reset(reset),
|
|
|
|
|
|
|
|
.data_in({equalizer_out_strobe, equalizer_out}),
|
|
|
|
.data_out({eq_out_stb_delayed, eq_out_i_delayed, eq_out_q_delayed})
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
|
|
ofdm_decoder ofdm_decoder_inst (
|
|
|
|
.clock(clock),
|
|
|
|
.reset(reset|ofdm_reset),
|
|
|
|
.enable(enable & ofdm_enable),
|
|
|
|
|
|
|
|
.sample_in({ofdm_in_i, ofdm_in_q}),
|
|
|
|
.sample_in_strobe(ofdm_in_stb),
|
2019-12-10 12:45:43 +00:00
|
|
|
.soft_decoding(soft_decoding),
|
2017-04-03 16:52:03 +00:00
|
|
|
|
|
|
|
.do_descramble(do_descramble),
|
|
|
|
.num_bits_to_decode(num_bits_to_decode),
|
2017-04-21 17:41:49 +00:00
|
|
|
.rate(pkt_rate),
|
2017-04-03 16:52:03 +00:00
|
|
|
|
|
|
|
.byte_out(byte_out),
|
|
|
|
.byte_out_strobe(byte_out_strobe),
|
|
|
|
|
|
|
|
.demod_out(demod_out),
|
|
|
|
.demod_out_strobe(demod_out_strobe),
|
|
|
|
|
2019-12-10 12:31:16 +00:00
|
|
|
.deinterleave_erase_out(deinterleave_erase_out),
|
|
|
|
.deinterleave_erase_out_strobe(deinterleave_erase_out_strobe),
|
2017-04-03 16:52:03 +00:00
|
|
|
|
|
|
|
.conv_decoder_out(conv_decoder_out),
|
|
|
|
.conv_decoder_out_stb(conv_decoder_out_stb),
|
|
|
|
|
|
|
|
.descramble_out(descramble_out),
|
|
|
|
.descramble_out_strobe(descramble_out_strobe)
|
|
|
|
);
|
|
|
|
|
|
|
|
ht_sig_crc crc_inst (
|
|
|
|
.clock(clock),
|
|
|
|
.enable(enable),
|
|
|
|
.reset(reset | crc_reset),
|
|
|
|
|
|
|
|
.bit(crc_in),
|
|
|
|
.input_strobe(crc_in_stb),
|
|
|
|
.crc(crc_out)
|
|
|
|
);
|
|
|
|
|
|
|
|
crc32 fcs_inst (
|
|
|
|
.clk(clock),
|
|
|
|
.crc_en(enable & fcs_enable),
|
|
|
|
.rst(reset | fcs_reset),
|
|
|
|
.data_in(byte_reversed),
|
|
|
|
.crc_out(pkt_fcs)
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
|
|
always @(posedge clock) begin
|
|
|
|
if (reset) begin
|
|
|
|
status_code <= E_OK;
|
|
|
|
state <= S_WAIT_POWER_TRIGGER;
|
|
|
|
old_state <= 0;
|
|
|
|
|
|
|
|
sync_short_reset <= 0;
|
|
|
|
|
|
|
|
sync_long_reset <= 0;
|
|
|
|
sync_long_enable <= 0;
|
|
|
|
|
|
|
|
byte_count <= 0;
|
2019-12-10 12:31:16 +00:00
|
|
|
byte_count_total <= 0;
|
2017-04-03 16:52:03 +00:00
|
|
|
|
2019-12-10 12:31:16 +00:00
|
|
|
demod_is_ongoing <= 0;
|
2017-04-21 17:41:49 +00:00
|
|
|
pkt_begin <= 0;
|
|
|
|
pkt_ht <= 0;
|
2019-12-10 12:31:16 +00:00
|
|
|
pkt_header_valid <= 0;
|
|
|
|
pkt_header_valid_strobe <= 0;
|
|
|
|
ht_unsupport <= 0;
|
2017-04-03 16:52:03 +00:00
|
|
|
|
|
|
|
rot_eq_count <= 0;
|
|
|
|
normal_eq_count <= 0;
|
|
|
|
abs_eq_i <= 0;
|
|
|
|
abs_eq_q <= 0;
|
|
|
|
|
|
|
|
do_descramble <= 0;
|
|
|
|
num_bits_to_decode <= 0;
|
|
|
|
short_gi <= 0;
|
2017-04-21 17:41:49 +00:00
|
|
|
pkt_rate <= 0;
|
2017-04-03 16:52:03 +00:00
|
|
|
|
|
|
|
equalizer_reset <= 0;
|
|
|
|
equalizer_enable <= 0;
|
|
|
|
ht_next <= 0;
|
|
|
|
|
2017-04-21 17:41:49 +00:00
|
|
|
pkt_len <= 0;
|
2019-12-10 12:31:16 +00:00
|
|
|
pkt_len_total <= 0;
|
2017-04-03 16:52:03 +00:00
|
|
|
|
|
|
|
ofdm_reset <= 0;
|
|
|
|
ofdm_enable <= 0;
|
|
|
|
ofdm_in_stb <= 0;
|
|
|
|
ofdm_in_i <= 0;
|
|
|
|
ofdm_in_q <= 0;
|
|
|
|
|
|
|
|
sample_count <= 0;
|
|
|
|
|
|
|
|
sync_long_out_count <= 0;
|
|
|
|
|
|
|
|
signal_bits <= 0;
|
2017-04-21 17:41:49 +00:00
|
|
|
legacy_sig_stb <= 0;
|
2017-04-03 16:52:03 +00:00
|
|
|
|
|
|
|
ht_sig1 <= 0;
|
|
|
|
ht_sig2 <= 0;
|
|
|
|
crc_in_stb <= 0;
|
|
|
|
crc_in <= 0;
|
|
|
|
crc_count <= 0;
|
|
|
|
crc_reset <= 0;
|
|
|
|
ht_sig_crc_ok <= 0;
|
2017-04-21 17:41:49 +00:00
|
|
|
ht_sig_stb <= 0;
|
2017-04-03 16:52:03 +00:00
|
|
|
|
|
|
|
fcs_out_strobe <= 0;
|
|
|
|
fcs_ok <= 0;
|
|
|
|
end else if (enable) begin
|
|
|
|
old_state <= state;
|
|
|
|
|
|
|
|
case(state)
|
|
|
|
S_WAIT_POWER_TRIGGER: begin
|
2019-12-10 12:31:16 +00:00
|
|
|
crc_reset <= 0;
|
|
|
|
short_gi <= 0;
|
|
|
|
demod_is_ongoing <= 0;
|
2017-04-03 16:52:03 +00:00
|
|
|
sync_long_enable <= 0;
|
|
|
|
equalizer_enable <= 0;
|
|
|
|
ofdm_enable <= 0;
|
2019-12-10 12:31:16 +00:00
|
|
|
ofdm_reset <= 0;
|
|
|
|
pkt_len_total <= 16'hffff;
|
2017-04-03 16:52:03 +00:00
|
|
|
|
|
|
|
if (power_trigger) begin
|
|
|
|
`ifdef DEBUG_PRINT
|
|
|
|
$display("Power triggered.");
|
|
|
|
`endif
|
|
|
|
sync_short_reset <= 1;
|
|
|
|
state <= S_SYNC_SHORT;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
S_SYNC_SHORT: begin
|
|
|
|
if (sync_short_reset) begin
|
|
|
|
sync_short_reset <= 0;
|
|
|
|
end
|
|
|
|
|
|
|
|
if (~power_trigger) begin
|
|
|
|
// power level drops before finding STS
|
|
|
|
state <= S_WAIT_POWER_TRIGGER;
|
|
|
|
end
|
|
|
|
|
|
|
|
if (short_preamble_detected) begin
|
|
|
|
`ifdef DEBUG_PRINT
|
|
|
|
$display("Short preamble detected");
|
|
|
|
`endif
|
|
|
|
sync_long_reset <= 1;
|
|
|
|
sync_long_enable <= 1;
|
|
|
|
sample_count <= 0;
|
|
|
|
state <= S_SYNC_LONG;
|
|
|
|
end
|
|
|
|
|
|
|
|
end
|
|
|
|
|
|
|
|
S_SYNC_LONG: begin
|
|
|
|
if (sync_long_reset) begin
|
|
|
|
sync_long_reset <= 0;
|
|
|
|
end
|
|
|
|
|
|
|
|
if (sample_in_strobe) begin
|
|
|
|
sample_count <= sample_count + 1;
|
|
|
|
end
|
|
|
|
if (sample_count > 320) begin
|
|
|
|
state <= S_WAIT_POWER_TRIGGER;
|
|
|
|
end
|
|
|
|
|
|
|
|
if (~power_trigger) begin
|
|
|
|
state <= S_WAIT_POWER_TRIGGER;
|
|
|
|
end
|
|
|
|
|
|
|
|
if (long_preamble_detected) begin
|
2019-12-10 12:31:16 +00:00
|
|
|
demod_is_ongoing <= 1;
|
2017-04-21 17:41:49 +00:00
|
|
|
pkt_rate <= {1'b0, 3'b0, 4'b1011};
|
2017-04-03 16:52:03 +00:00
|
|
|
do_descramble <= 0;
|
|
|
|
num_bits_to_decode <= 48;
|
|
|
|
|
|
|
|
ofdm_reset <= 1;
|
|
|
|
ofdm_enable <= 1;
|
|
|
|
|
|
|
|
equalizer_enable <= 1;
|
|
|
|
equalizer_reset <= 1;
|
|
|
|
|
|
|
|
byte_count <= 0;
|
2019-12-10 12:31:16 +00:00
|
|
|
byte_count_total <= 0;
|
2017-04-03 16:52:03 +00:00
|
|
|
state <= S_DECODE_SIGNAL;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
S_DECODE_SIGNAL: begin
|
2019-12-10 12:31:16 +00:00
|
|
|
ofdm_reset <= 0;
|
2017-04-03 16:52:03 +00:00
|
|
|
|
|
|
|
if (equalizer_reset) begin
|
|
|
|
equalizer_reset <= 0;
|
|
|
|
end
|
|
|
|
|
|
|
|
ofdm_in_stb <= equalizer_out_strobe;
|
|
|
|
ofdm_in_i <= eq_out_i;
|
|
|
|
ofdm_in_q <= eq_out_q;
|
|
|
|
|
|
|
|
if (byte_out_strobe) begin
|
|
|
|
signal_bits <= {byte_out, signal_bits[23:8]};
|
|
|
|
byte_count <= byte_count + 1;
|
2019-12-10 12:31:16 +00:00
|
|
|
byte_count_total <= byte_count_total + 1;
|
2017-04-03 16:52:03 +00:00
|
|
|
end
|
|
|
|
|
|
|
|
if (byte_count == 3) begin
|
|
|
|
byte_count <= 0;
|
|
|
|
`ifdef DEBUG_PRINT
|
2017-04-21 17:41:49 +00:00
|
|
|
$display("[SIGNAL] rate = %04b, ", legacy_rate,
|
|
|
|
"length = %012b (%d), ", legacy_len, legacy_len,
|
|
|
|
"parity = %b, ", legacy_sig_parity,
|
|
|
|
"tail = %6b", legacy_sig_tail);
|
2017-04-03 16:52:03 +00:00
|
|
|
`endif
|
2019-12-10 12:31:16 +00:00
|
|
|
|
|
|
|
num_bits_to_decode <= (22+(legacy_len<<3))<<1;
|
|
|
|
pkt_rate <= {1'b0, 3'b0, legacy_rate};
|
|
|
|
pkt_len <= legacy_len;
|
|
|
|
pkt_len_total <= legacy_len+3;
|
|
|
|
|
2017-04-03 16:52:03 +00:00
|
|
|
ofdm_reset <= 1;
|
|
|
|
state <= S_CHECK_SIGNAL;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
S_CHECK_SIGNAL: begin
|
2017-04-21 17:41:49 +00:00
|
|
|
if (~legacy_sig_parity_ok) begin
|
2019-12-10 12:31:16 +00:00
|
|
|
pkt_header_valid_strobe <= 1;
|
2017-04-03 16:52:03 +00:00
|
|
|
status_code <= E_PARITY_FAIL;
|
|
|
|
state <= S_SIGNAL_ERROR;
|
2017-04-21 17:41:49 +00:00
|
|
|
end else if (legacy_sig_rsvd) begin
|
2019-12-10 12:31:16 +00:00
|
|
|
pkt_header_valid_strobe <= 1;
|
2017-04-03 16:52:03 +00:00
|
|
|
status_code <= E_WRONG_RSVD;
|
|
|
|
state <= S_SIGNAL_ERROR;
|
2017-04-21 17:41:49 +00:00
|
|
|
end else if (|legacy_sig_tail) begin
|
2019-12-10 12:31:16 +00:00
|
|
|
pkt_header_valid_strobe <= 1;
|
2017-04-03 16:52:03 +00:00
|
|
|
status_code <= E_WRONG_TAIL;
|
|
|
|
state <= S_SIGNAL_ERROR;
|
2019-12-10 12:31:16 +00:00
|
|
|
end else if (legacy_rate[3]==0) begin
|
|
|
|
pkt_header_valid_strobe <= 1;
|
|
|
|
status_code <= E_UNSUPPORTED_RATE;
|
|
|
|
state <= S_SIGNAL_ERROR;
|
2017-04-03 16:52:03 +00:00
|
|
|
end else begin
|
2017-04-21 17:41:49 +00:00
|
|
|
legacy_sig_stb <= 1;
|
2017-04-03 16:52:03 +00:00
|
|
|
status_code <= E_OK;
|
2017-04-21 17:41:49 +00:00
|
|
|
if (legacy_rate == 4'b1011) begin
|
2017-04-03 16:52:03 +00:00
|
|
|
abs_eq_i <= 0;
|
|
|
|
abs_eq_q <= 0;
|
|
|
|
rot_eq_count <= 0;
|
|
|
|
normal_eq_count <= 0;
|
|
|
|
state <= S_DETECT_HT;
|
|
|
|
end else begin
|
2019-12-10 12:31:16 +00:00
|
|
|
//num_bits_to_decode <= (legacy_len+3)<<4;
|
2017-04-03 16:52:03 +00:00
|
|
|
do_descramble <= 1;
|
|
|
|
ofdm_reset <= 1;
|
2019-12-10 12:31:16 +00:00
|
|
|
pkt_header_valid <= 1;
|
|
|
|
pkt_header_valid_strobe <= 1;
|
2017-04-21 17:41:49 +00:00
|
|
|
pkt_begin <= 1;
|
|
|
|
pkt_ht <= 0;
|
2017-04-03 16:52:03 +00:00
|
|
|
state <= S_DECODE_DATA;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
S_SIGNAL_ERROR: begin
|
2019-12-10 12:31:16 +00:00
|
|
|
pkt_header_valid_strobe <= 0;
|
|
|
|
byte_count <= 0;
|
|
|
|
byte_count_total <= 0;
|
2017-04-03 16:52:03 +00:00
|
|
|
state <= S_WAIT_POWER_TRIGGER;
|
|
|
|
end
|
|
|
|
|
|
|
|
S_DETECT_HT: begin
|
2017-04-21 17:41:49 +00:00
|
|
|
legacy_sig_stb <= 0;
|
2019-12-10 12:31:16 +00:00
|
|
|
ofdm_reset <= 1;
|
2017-04-03 16:52:03 +00:00
|
|
|
|
|
|
|
if (equalizer_out_strobe) begin
|
|
|
|
abs_eq_i <= eq_out_i[15]? ~eq_out_i+1: eq_out_i;
|
|
|
|
abs_eq_q <= eq_out_q[15]? ~eq_out_q+1: eq_out_q;
|
|
|
|
if (abs_eq_q > abs_eq_i) begin
|
|
|
|
rot_eq_count <= rot_eq_count + 1;
|
|
|
|
end else begin
|
|
|
|
normal_eq_count <= normal_eq_count + 1;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
if (rot_eq_count >= 4) begin
|
|
|
|
// HT-SIG detected
|
|
|
|
num_bits_to_decode <= 96;
|
|
|
|
do_descramble <= 0;
|
|
|
|
state <= S_HT_SIGNAL;
|
|
|
|
end else if (normal_eq_count > 4) begin
|
2019-12-10 12:31:16 +00:00
|
|
|
//num_bits_to_decode <= (legacy_len+3)<<4;
|
2017-04-03 16:52:03 +00:00
|
|
|
do_descramble <= 1;
|
2019-12-10 12:31:16 +00:00
|
|
|
pkt_header_valid <= 1;
|
|
|
|
pkt_header_valid_strobe <= 1;
|
2017-04-21 17:41:49 +00:00
|
|
|
pkt_begin <= 1;
|
|
|
|
pkt_ht <= 0;
|
2017-04-03 16:52:03 +00:00
|
|
|
state <= S_DECODE_DATA;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
S_HT_SIGNAL: begin
|
2019-12-10 12:31:16 +00:00
|
|
|
ofdm_reset <= 0;
|
2017-04-03 16:52:03 +00:00
|
|
|
|
|
|
|
ofdm_in_stb <= eq_out_stb_delayed;
|
|
|
|
// rotate clockwise by 90 degree
|
|
|
|
ofdm_in_i <= eq_out_q_delayed;
|
|
|
|
ofdm_in_q <= ~eq_out_i_delayed+1;
|
|
|
|
|
|
|
|
if (byte_out_strobe) begin
|
|
|
|
if (byte_count < 3) begin
|
|
|
|
ht_sig1 <= {byte_out, ht_sig1[23:8]};
|
|
|
|
end else begin
|
|
|
|
ht_sig2 <= {byte_out, ht_sig2[23:8]};
|
|
|
|
end
|
|
|
|
byte_count <= byte_count + 1;
|
2019-12-10 12:31:16 +00:00
|
|
|
byte_count_total <= byte_count_total + 1;
|
2017-04-03 16:52:03 +00:00
|
|
|
end
|
|
|
|
|
|
|
|
if (byte_count == 6) begin
|
|
|
|
byte_count <= 0;
|
|
|
|
`ifdef DEBUG_PRINT
|
2017-04-21 17:41:49 +00:00
|
|
|
$display("[HT SIGNAL] mcs = %07b (%d), ", ht_mcs, ht_mcs,
|
|
|
|
"CBW: %d, ", ht_cbw? 40: 20,
|
2017-04-03 16:52:03 +00:00
|
|
|
"length = %012b (%d), ", ht_len, ht_len,
|
|
|
|
"rsvd = %d, ", ht_rsvd,
|
2017-04-21 17:41:49 +00:00
|
|
|
"aggr = %d, ", ht_aggregation,
|
|
|
|
"stbd = %02b, ", ht_stbc,
|
|
|
|
"fec = %d, ", ht_fec_coding,
|
2017-04-03 16:52:03 +00:00
|
|
|
"sgi = %d, ", ht_sgi,
|
2017-04-21 17:41:49 +00:00
|
|
|
"num_ext = %d, ", ht_num_ext,
|
2017-04-03 16:52:03 +00:00
|
|
|
"crc = %08b, ", crc,
|
|
|
|
"tail = %06b", ht_sig_tail);
|
|
|
|
`endif
|
2019-12-10 12:31:16 +00:00
|
|
|
|
|
|
|
num_bits_to_decode <= (22+(ht_len<<3))<<1;
|
|
|
|
pkt_rate <= {1'b1, ht_mcs};
|
|
|
|
pkt_len <= ht_len;
|
|
|
|
pkt_len_total <= ht_len+3+6; //(6 bytes for 3 byte HT-SIG1 and 3 byte HT-SIG2)
|
|
|
|
|
2017-04-03 16:52:03 +00:00
|
|
|
crc_count <= 0;
|
|
|
|
crc_reset <= 1;
|
|
|
|
crc_in_stb <= 0;
|
|
|
|
ht_sig_crc_ok <= 0;
|
|
|
|
state <= S_CHECK_HT_SIG_CRC;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
S_CHECK_HT_SIG_CRC: begin
|
2019-12-10 12:31:16 +00:00
|
|
|
ofdm_reset <= 1;
|
2017-04-03 16:52:03 +00:00
|
|
|
crc_reset <= 0;
|
|
|
|
crc_count <= crc_count + 1;
|
|
|
|
|
|
|
|
if (crc_count < 24) begin
|
|
|
|
crc_in_stb <= 1;
|
|
|
|
crc_in <= ht_sig1[crc_count];
|
|
|
|
end else if (crc_count < 34) begin
|
|
|
|
crc_in_stb <= 1;
|
|
|
|
crc_in <= ht_sig2[crc_count-24];
|
|
|
|
end else if (crc_count == 34) begin
|
|
|
|
crc_in_stb <= 0;
|
|
|
|
end else if (crc_count == 35) begin
|
2019-12-10 12:31:16 +00:00
|
|
|
ht_sig_stb <= 1;
|
|
|
|
pkt_ht <= 1;
|
2017-04-03 16:52:03 +00:00
|
|
|
if (crc_out ^ crc) begin
|
2019-12-10 12:31:16 +00:00
|
|
|
pkt_header_valid_strobe <= 1;
|
2017-04-03 16:52:03 +00:00
|
|
|
status_code <= E_WRONG_CRC;
|
|
|
|
state <= S_HT_SIG_ERROR;
|
|
|
|
end else begin
|
|
|
|
`ifdef DEBUG_PRINT
|
|
|
|
$display("[HT SIGNAL] CRC OK");
|
|
|
|
`endif
|
|
|
|
ht_sig_crc_ok <= 1;
|
|
|
|
state <= S_CHECK_HT_SIG;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
S_CHECK_HT_SIG: begin
|
2019-12-10 12:31:16 +00:00
|
|
|
ofdm_reset <= 1;
|
2017-04-21 17:41:49 +00:00
|
|
|
ht_sig_stb <= 0;
|
2019-12-10 12:31:16 +00:00
|
|
|
|
|
|
|
pkt_header_valid <= 1;
|
|
|
|
pkt_header_valid_strobe <= 1;
|
2017-04-21 17:41:49 +00:00
|
|
|
if (ht_mcs > 7) begin
|
2019-12-10 12:31:16 +00:00
|
|
|
ht_unsupport <= 1;
|
2017-04-03 16:52:03 +00:00
|
|
|
status_code <= E_UNSUPPORTED_MCS;
|
|
|
|
state <= S_HT_SIG_ERROR;
|
2017-04-21 17:41:49 +00:00
|
|
|
end else if (ht_cbw) begin
|
2019-12-10 12:31:16 +00:00
|
|
|
ht_unsupport <= 1;
|
2017-04-03 16:52:03 +00:00
|
|
|
status_code <= E_UNSUPPORTED_CBW;
|
|
|
|
state <= S_HT_SIG_ERROR;
|
|
|
|
end else if (ht_rsvd == 0) begin
|
2019-12-10 12:31:16 +00:00
|
|
|
ht_unsupport <= 1;
|
2017-04-03 16:52:03 +00:00
|
|
|
status_code <= E_HT_WRONG_RSVD;
|
|
|
|
state <= S_HT_SIG_ERROR;
|
2017-04-21 17:41:49 +00:00
|
|
|
end else if (ht_stbc != 0) begin
|
2019-12-10 12:31:16 +00:00
|
|
|
ht_unsupport <= 1;
|
2017-04-03 16:52:03 +00:00
|
|
|
status_code <= E_UNSUPPORTED_STBC;
|
|
|
|
state <= S_HT_SIG_ERROR;
|
2017-04-21 17:41:49 +00:00
|
|
|
end else if (ht_fec_coding) begin
|
2019-12-10 12:31:16 +00:00
|
|
|
ht_unsupport <= 1;
|
2017-04-03 16:52:03 +00:00
|
|
|
status_code <= E_UNSUPPORTED_FEC;
|
|
|
|
state <= S_HT_SIG_ERROR;
|
2019-12-10 12:31:16 +00:00
|
|
|
// end else if (ht_sgi) begin // seems like it supports ht short_gi, we should proceed
|
|
|
|
// ht_unsupport <= 1;
|
|
|
|
// status_code <= E_UNSUPPORTED_SGI;
|
|
|
|
// state <= S_HT_SIG_ERROR;
|
2017-04-21 17:41:49 +00:00
|
|
|
end else if (ht_num_ext != 0) begin
|
2019-12-10 12:31:16 +00:00
|
|
|
ht_unsupport <= 1;
|
2017-04-03 16:52:03 +00:00
|
|
|
status_code <= E_UNSUPPORTED_SPATIAL;
|
|
|
|
state <= S_HT_SIG_ERROR;
|
|
|
|
end else if (ht_sig_tail != 0) begin
|
2019-12-10 12:31:16 +00:00
|
|
|
ht_unsupport <= 1;
|
2017-04-03 16:52:03 +00:00
|
|
|
status_code <= E_HT_WRONG_TAIL;
|
|
|
|
state <= S_HT_SIG_ERROR;
|
|
|
|
end else begin
|
|
|
|
sync_long_out_count <= 0;
|
|
|
|
state <= S_HT_STS;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
S_HT_SIG_ERROR: begin
|
2019-12-10 12:31:16 +00:00
|
|
|
ht_unsupport <= 0;
|
|
|
|
pkt_header_valid <= 0;
|
|
|
|
pkt_header_valid_strobe <= 0;
|
|
|
|
byte_count <= 0;
|
|
|
|
byte_count_total <= 0;
|
2017-04-21 17:41:49 +00:00
|
|
|
ht_sig_stb <= 0;
|
2017-04-03 16:52:03 +00:00
|
|
|
state <= S_WAIT_POWER_TRIGGER;
|
|
|
|
end
|
|
|
|
|
|
|
|
S_HT_STS: begin
|
2019-12-10 12:31:16 +00:00
|
|
|
pkt_header_valid <= 0;
|
|
|
|
pkt_header_valid_strobe <= 0;
|
2017-04-03 16:52:03 +00:00
|
|
|
if (sync_long_out_strobe) begin
|
|
|
|
sync_long_out_count <= sync_long_out_count + 1;
|
|
|
|
end
|
|
|
|
if (sync_long_out_count == 64) begin
|
|
|
|
sync_long_out_count <= 0;
|
|
|
|
ht_next <= 1;
|
|
|
|
state <= S_HT_LTS;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
S_HT_LTS: begin
|
|
|
|
short_gi <= ht_sgi;
|
|
|
|
if (sync_long_out_strobe) begin
|
|
|
|
sync_long_out_count <= sync_long_out_count + 1;
|
|
|
|
end
|
|
|
|
if (sync_long_out_count == 64) begin
|
|
|
|
ht_next <= 0;
|
2019-12-10 12:31:16 +00:00
|
|
|
//num_bits_to_decode <= (ht_len+3)<<4;
|
2017-04-03 16:52:03 +00:00
|
|
|
do_descramble <= 1;
|
|
|
|
ofdm_reset <= 1;
|
2017-04-21 17:41:49 +00:00
|
|
|
pkt_begin <= 1;
|
2017-04-03 16:52:03 +00:00
|
|
|
state <= S_DECODE_DATA;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
S_DECODE_DATA: begin
|
2017-04-21 17:41:49 +00:00
|
|
|
pkt_begin <= 0;
|
|
|
|
legacy_sig_stb <= 0;
|
2017-04-03 16:52:03 +00:00
|
|
|
|
2019-12-10 12:31:16 +00:00
|
|
|
pkt_header_valid <= 0;
|
|
|
|
pkt_header_valid_strobe <= 0;
|
|
|
|
|
|
|
|
ofdm_reset <= 0;
|
2017-04-03 16:52:03 +00:00
|
|
|
|
|
|
|
ofdm_in_stb <= eq_out_stb_delayed;
|
|
|
|
ofdm_in_i <= eq_out_i_delayed;
|
|
|
|
ofdm_in_q <= eq_out_q_delayed;
|
|
|
|
|
|
|
|
if (byte_out_strobe) begin
|
|
|
|
`ifdef DEBUG_PRINT
|
2017-04-21 17:41:49 +00:00
|
|
|
$display("[BYTE] [%4d / %-4d] %02x", byte_count+1, pkt_len,
|
2017-04-03 16:52:03 +00:00
|
|
|
byte_out);
|
|
|
|
`endif
|
|
|
|
byte_count <= byte_count + 1;
|
2019-12-10 12:31:16 +00:00
|
|
|
byte_count_total <= byte_count_total + 1;
|
2017-04-03 16:52:03 +00:00
|
|
|
end
|
|
|
|
|
2017-04-21 17:41:49 +00:00
|
|
|
if (byte_count >= pkt_len) begin
|
2017-04-03 16:52:03 +00:00
|
|
|
fcs_out_strobe <= 1;
|
2019-12-10 12:31:16 +00:00
|
|
|
byte_count <= 0;
|
|
|
|
byte_count_total <= 0;
|
2017-04-03 16:52:03 +00:00
|
|
|
if (pkt_fcs == EXPECTED_FCS) begin
|
|
|
|
fcs_ok <= 1;
|
|
|
|
status_code <= E_OK;
|
|
|
|
end else begin
|
|
|
|
fcs_ok <= 0;
|
|
|
|
status_code <= E_WRONG_FCS;
|
|
|
|
end
|
|
|
|
state <= S_DECODE_DONE;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
S_DECODE_DONE: begin
|
|
|
|
`ifdef DEBUG_PRINT
|
|
|
|
$display("===== PACKET DECODE DONE =====");
|
|
|
|
if (status_code == E_OK) begin
|
|
|
|
$display("FCS CORRECT");
|
|
|
|
end else begin
|
|
|
|
$display("FCS WRONG");
|
|
|
|
end
|
|
|
|
`endif
|
|
|
|
fcs_out_strobe <= 0;
|
2019-12-10 12:31:16 +00:00
|
|
|
fcs_ok <= 0;
|
2017-04-03 16:52:03 +00:00
|
|
|
state <= S_WAIT_POWER_TRIGGER;
|
|
|
|
end
|
|
|
|
|
|
|
|
default: begin
|
2019-12-10 12:31:16 +00:00
|
|
|
byte_count <= 0;
|
|
|
|
byte_count_total <= 0;
|
2017-04-03 16:52:03 +00:00
|
|
|
state <= S_WAIT_POWER_TRIGGER;
|
|
|
|
end
|
|
|
|
endcase
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
endmodule
|