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29 lines
890 B
ReStructuredText
29 lines
890 B
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OpenOFDM
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========
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This project contains a Verilog implementation of 802.11 OFDM PHY decoder.
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Features are:
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- Fully synthesizable (tested on Ettus Research USRP N210 platform)
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- Full support for legacy 802.11a/g
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- Support 802.11n for MCS 0 - 7 @ 20 MHz bandwidth
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- Cross validation with included Python decoder
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Environment Setup
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-----------------
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This project has the following dependencies:
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- `Icarus Verilog <http://iverilog.icarus.com/>`_: for compiling Verilog files and simulation.
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- `GtkWave <http://iverilog.icarus.com/>`_: for wave form visualization.
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Input and Output
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----------------
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In a nutshell, the top level ``dot11`` Verilog module takes 32-bit I/Q samples
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(16-bit each) as input, and output decoded bytes in 802.11 packet. The sampling
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rate is 20 MSPS and the clock rate is 100 MHz. This means this module expects
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one pair of I/Q sample every 5 clock ticks.
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