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https://github.com/jhshi/openofdm.git
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45 lines
689 B
Plaintext
45 lines
689 B
Plaintext
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-y ./Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/
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-y ./Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/
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dot11.v
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sync_short.v
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power_trigger.v
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moving_avg.v
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delay_sample.v
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complex_to_mag.v
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divider.v
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complex_to_mag_sq.v
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sync_long.v
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stage_mult.v
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ofdm_decoder.v
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phase.v
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rotate.v
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equalizer.v
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complex_mult.v
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calc_mean.v
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deinterleave.v
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demodulate.v
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descramble.v
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bits_to_bytes.v
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delayT.v
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ht_sig_crc.v
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rate_to_idx.v
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crc32.v
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./usrp2/setting_reg.v
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./usrp2/ram_2port.v
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./coregen/xfft_v7_1.v
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./coregen/complex_multiplier.v
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./coregen/viterbi_v7_0.v
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./coregen/div_gen_v3_0.v
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./coregen/deinter_lut.v
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./coregen/atan_lut.v
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./coregen/rot_lut.v
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./Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MULT18X18S.v
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