-y ./Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/
-y ./Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/

dot11.v

sync_short.v
power_trigger.v
moving_avg.v
delay_sample.v
complex_to_mag.v
divider.v
complex_to_mag_sq.v

sync_long.v
stage_mult.v

ofdm_decoder.v
phase.v
rotate.v
equalizer.v
complex_mult.v
calc_mean.v
deinterleave.v
demodulate.v
descramble.v
bits_to_bytes.v

delayT.v
ht_sig_crc.v
rate_to_idx.v
crc32.v

./usrp2/setting_reg.v
./usrp2/ram_2port.v

./coregen/xfft_v7_1.v
./coregen/complex_multiplier.v
./coregen/viterbi_v7_0.v
./coregen/div_gen_v3_0.v
./coregen/deinter_lut.v
./coregen/atan_lut.v
./coregen/rot_lut.v

./Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MULT18X18S.v
