##############################################################
#
# Xilinx Core Generator version 12.2
# Date: Thu Sep 15 18:36:40 2016
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc3sd3400a
SET devicefamily = spartan3adsp
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fg676
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -5
SET verilogsim = true
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Divider_Generator family Xilinx,_Inc. 3.0
# END Select
# BEGIN Parameters
CSET algorithm_type=Radix2
CSET ce=false
CSET clocks_per_division=1
CSET component_name=div_gen_v3_0
CSET divide_by_zero_detect=false
CSET dividend_and_quotient_width=32
CSET divisor_width=24
CSET fractional_width=24
CSET latency=36
CSET latency_configuration=Automatic
CSET operand_sign=Signed
CSET remainder_type=Remainder
CSET sclr=false
CSET sclr_ce_priority=SCLR_overrides_CE
# END Parameters
GENERATE
# CRC: 9bd259e4
