/*******************************************************************************
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// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
complex_multiplier YourInstanceName (
	.ar(ar), // Bus [15 : 0] 
	.ai(ai), // Bus [15 : 0] 
	.br(br), // Bus [15 : 0] 
	.bi(bi), // Bus [15 : 0] 
	.clk(clk),
	.pr(pr), // Bus [31 : 0] 
	.pi(pi)); // Bus [31 : 0] 

// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file complex_multiplier.v when simulating
// the core, complex_multiplier. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

