--------------------------------------------------------------------------------
-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: M.63c
--  \   \         Application: netgen
--  /   /         Filename: div_gen_v3_0.vhd
-- /___/   /\     Timestamp: Thu Sep 15 14:36:33 2016
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -w -sim -ofmt vhdl ./tmp/_cg/div_gen_v3_0.ngc ./tmp/_cg/div_gen_v3_0.vhd 
-- Device	: 3sd3400afg676-5
-- Input file	: ./tmp/_cg/div_gen_v3_0.ngc
-- Output file	: ./tmp/_cg/div_gen_v3_0.vhd
-- # of Entities	: 1
-- Design Name	: div_gen_v3_0
-- Xilinx	: /opt/Xilinx/12.2/ISE_DS/ISE/
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Command Line Tools User Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------


-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity div_gen_v3_0 is
  port (
    rfd : out STD_LOGIC; 
    clk : in STD_LOGIC := 'X'; 
    dividend : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    quotient : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    divisor : in STD_LOGIC_VECTOR ( 23 downto 0 ); 
    fractional : out STD_LOGIC_VECTOR ( 23 downto 0 ) 
  );
end div_gen_v3_0;

architecture STRUCTURE of div_gen_v3_0 is
  signal NlwRenamedSig_OI_rfd : STD_LOGIC; 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_1_5794 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_2_5793 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_0_5792 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_3_5791 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_4_5790 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_5_5789 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_6_5788 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_8_5787 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_9_5786 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_7_5785 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_10_5784 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_11_5783 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_12_5782 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_13_5781 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_15_5780 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_16_5779 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_14_5778 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_17_5777 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_18_5776 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_19_5775 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_20_5774 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_21_5773 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_22_5772 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_23_5771 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_0_5770 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_1_5769 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_2_5768 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_3_5767 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_4_5766 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_6_5765 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_7_5764 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_5_5763 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_8_5762 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_9_5761 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_10_5760 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_11_5759 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_13_5758 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_14_5757 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_12_5756 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_15_5755 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_16_5754 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_17_5753 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_18_5752 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_20_5751 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_21_5750 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_19_5749 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_22_5748 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_23_5747 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_24_5746 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_25_5745 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_26_5744 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_27_5743 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_28_5742 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_29_5741 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_30_5740 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_31_5739 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_Mshreg_opt_has_pipe_pipe_32_0_1_5738 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_Mshreg_opt_has_pipe_pipe_32_0_0_5737 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_Mshreg_opt_has_pipe_pipe_32_1_1_5736 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_Mshreg_opt_has_pipe_pipe_32_1_0_5735 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_4_5734 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_3_5733 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_2_5732 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_2_5731 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_4_5730 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_3_5729 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_1_5725 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_1_5724 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_0_rt_5722 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_quot_det : STD_LOGIC; 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_0_rt_5650 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_26_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_27_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_28_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_29_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_30_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_26_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_27_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_28_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_29_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_26_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_27_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_28_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_26_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_27_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_26_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_27_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_27_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_28_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_27_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_27_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_28_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_28_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_29_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_29_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_30_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_27_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_28_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_29_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_30_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_31_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_inv_o : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_0_rt_281 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_0_rt_211 : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_msb_divisor_sync_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_msb_dividend_sync_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_msb_divisor_start_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_msb_dividend_start_opt_has_pipe_first_q : STD_LOGIC;
 
  signal BU2_divide_by_zero : STD_LOGIC; 
  signal NLW_VCC_P_UNCONNECTED : STD_LOGIC; 
  signal NLW_GND_G_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_Mshreg_opt_has_pipe_pipe_32_0_0_Q_UNCONNECTED : STD_LOGIC;
 
  signal NLW_BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_Mshreg_opt_has_pipe_pipe_32_1_0_Q_UNCONNECTED : STD_LOGIC;
 
  signal dividend_2 : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal divisor_3 : STD_LOGIC_VECTOR ( 23 downto 0 ); 
  signal quotient_4 : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal fractional_5 : STD_LOGIC_VECTOR ( 23 downto 0 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i : STD_LOGIC_VECTOR ( 23 downto 0 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a : STD_LOGIC_VECTOR ( 23 downto 1 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy : STD_LOGIC_VECTOR ( 22 downto 0 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a : STD_LOGIC_VECTOR ( 31 downto 1 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy : STD_LOGIC_VECTOR ( 30 downto 0 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q : STD_LOGIC_VECTOR ( 24 downto 0 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di : STD_LOGIC_VECTOR ( 24 downto 0 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple : STD_LOGIC_VECTOR ( 24 downto 0 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum : STD_LOGIC_VECTOR ( 23 downto 0 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple : STD_LOGIC_VECTOR ( 24 downto 0 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o : STD_LOGIC_VECTOR ( 30 downto 0 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q : STD_LOGIC_VECTOR ( 23 downto 0 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi : STD_LOGIC_VECTOR ( 31 downto 1 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_first_q : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_32 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i : STD_LOGIC_VECTOR ( 23 downto 0 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a : STD_LOGIC_VECTOR ( 22 downto 1 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy : STD_LOGIC_VECTOR ( 22 downto 0 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a : STD_LOGIC_VECTOR ( 30 downto 1 ); 
  signal BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy : STD_LOGIC_VECTOR ( 30 downto 0 ); 
begin
  dividend_2(31) <= dividend(31);
  dividend_2(30) <= dividend(30);
  dividend_2(29) <= dividend(29);
  dividend_2(28) <= dividend(28);
  dividend_2(27) <= dividend(27);
  dividend_2(26) <= dividend(26);
  dividend_2(25) <= dividend(25);
  dividend_2(24) <= dividend(24);
  dividend_2(23) <= dividend(23);
  dividend_2(22) <= dividend(22);
  dividend_2(21) <= dividend(21);
  dividend_2(20) <= dividend(20);
  dividend_2(19) <= dividend(19);
  dividend_2(18) <= dividend(18);
  dividend_2(17) <= dividend(17);
  dividend_2(16) <= dividend(16);
  dividend_2(15) <= dividend(15);
  dividend_2(14) <= dividend(14);
  dividend_2(13) <= dividend(13);
  dividend_2(12) <= dividend(12);
  dividend_2(11) <= dividend(11);
  dividend_2(10) <= dividend(10);
  dividend_2(9) <= dividend(9);
  dividend_2(8) <= dividend(8);
  dividend_2(7) <= dividend(7);
  dividend_2(6) <= dividend(6);
  dividend_2(5) <= dividend(5);
  dividend_2(4) <= dividend(4);
  dividend_2(3) <= dividend(3);
  dividend_2(2) <= dividend(2);
  dividend_2(1) <= dividend(1);
  dividend_2(0) <= dividend(0);
  quotient(31) <= quotient_4(31);
  quotient(30) <= quotient_4(30);
  quotient(29) <= quotient_4(29);
  quotient(28) <= quotient_4(28);
  quotient(27) <= quotient_4(27);
  quotient(26) <= quotient_4(26);
  quotient(25) <= quotient_4(25);
  quotient(24) <= quotient_4(24);
  quotient(23) <= quotient_4(23);
  quotient(22) <= quotient_4(22);
  quotient(21) <= quotient_4(21);
  quotient(20) <= quotient_4(20);
  quotient(19) <= quotient_4(19);
  quotient(18) <= quotient_4(18);
  quotient(17) <= quotient_4(17);
  quotient(16) <= quotient_4(16);
  quotient(15) <= quotient_4(15);
  quotient(14) <= quotient_4(14);
  quotient(13) <= quotient_4(13);
  quotient(12) <= quotient_4(12);
  quotient(11) <= quotient_4(11);
  quotient(10) <= quotient_4(10);
  quotient(9) <= quotient_4(9);
  quotient(8) <= quotient_4(8);
  quotient(7) <= quotient_4(7);
  quotient(6) <= quotient_4(6);
  quotient(5) <= quotient_4(5);
  quotient(4) <= quotient_4(4);
  quotient(3) <= quotient_4(3);
  quotient(2) <= quotient_4(2);
  quotient(1) <= quotient_4(1);
  quotient(0) <= quotient_4(0);
  divisor_3(23) <= divisor(23);
  divisor_3(22) <= divisor(22);
  divisor_3(21) <= divisor(21);
  divisor_3(20) <= divisor(20);
  divisor_3(19) <= divisor(19);
  divisor_3(18) <= divisor(18);
  divisor_3(17) <= divisor(17);
  divisor_3(16) <= divisor(16);
  divisor_3(15) <= divisor(15);
  divisor_3(14) <= divisor(14);
  divisor_3(13) <= divisor(13);
  divisor_3(12) <= divisor(12);
  divisor_3(11) <= divisor(11);
  divisor_3(10) <= divisor(10);
  divisor_3(9) <= divisor(9);
  divisor_3(8) <= divisor(8);
  divisor_3(7) <= divisor(7);
  divisor_3(6) <= divisor(6);
  divisor_3(5) <= divisor(5);
  divisor_3(4) <= divisor(4);
  divisor_3(3) <= divisor(3);
  divisor_3(2) <= divisor(2);
  divisor_3(1) <= divisor(1);
  divisor_3(0) <= divisor(0);
  rfd <= NlwRenamedSig_OI_rfd;
  fractional(23) <= fractional_5(23);
  fractional(22) <= fractional_5(22);
  fractional(21) <= fractional_5(21);
  fractional(20) <= fractional_5(20);
  fractional(19) <= fractional_5(19);
  fractional(18) <= fractional_5(18);
  fractional(17) <= fractional_5(17);
  fractional(16) <= fractional_5(16);
  fractional(15) <= fractional_5(15);
  fractional(14) <= fractional_5(14);
  fractional(13) <= fractional_5(13);
  fractional(12) <= fractional_5(12);
  fractional(11) <= fractional_5(11);
  fractional(10) <= fractional_5(10);
  fractional(9) <= fractional_5(9);
  fractional(8) <= fractional_5(8);
  fractional(7) <= fractional_5(7);
  fractional(6) <= fractional_5(6);
  fractional(5) <= fractional_5(5);
  fractional(4) <= fractional_5(4);
  fractional(3) <= fractional_5(3);
  fractional(2) <= fractional_5(2);
  fractional(1) <= fractional_5(1);
  fractional(0) <= fractional_5(0);
  VCC_0 : VCC
    port map (
      P => NLW_VCC_P_UNCONNECTED
    );
  GND_1 : GND
    port map (
      G => NLW_GND_G_UNCONNECTED
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_1_5794
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_1 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(1),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_1_5794

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_2_5793
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_2 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(2),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_2_5793

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_0_5792
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_0 : 
SRL16
    generic map(
      INIT => X"0001"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(0),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_0_5792

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_3_5791
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_3 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(3),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_3_5791

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_4_5790
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_4 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(4),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_4_5790

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_5_5789
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_5 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(5),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_5_5789

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_6_5788
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_6 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(6),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_6_5788

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_8_5787
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_8 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(8),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_8_5787

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_9_5786
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_9 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(9),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_9_5786

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_7_5785
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_7 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(7),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_7_5785

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_10_5784
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_10 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(10),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_10_5784

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_11_5783
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_11 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(11),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_11_5783

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_12_5782
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_12 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(12),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_12_5782

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_13_5781
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_13 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(13),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_13_5781

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_15_5780
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_15 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(15),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_15_5780

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_16_5779
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_16 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(16),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_16_5779

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_14_5778
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_14 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(14),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_14_5778

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_17_5777
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_17 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(17),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_17_5777

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_18_5776
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_18 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(18),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_18_5776

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_19_5775
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_19 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(19),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_19_5775

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_20_5774
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_20 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(20),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_20_5774

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_21_5773
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_21 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(21),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_21_5773

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_22_5772
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_22 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(22),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_22_5772

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_23_5771
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_23 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(23),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_Mshreg_opt_has_pipe_first_q_23_5771

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_0_5770
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_0 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(0),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_0_5770

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_1_5769
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_1 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(1),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_1_5769

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_2_5768
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_2 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(2),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_2_5768

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_3_5767
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_3 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(3),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_3_5767

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_4_5766
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_4 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(4),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_4_5766

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_6_5765
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_6 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(6),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_6_5765

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_7_5764
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_7 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(7),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_7_5764

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_5_5763
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_5 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(5),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_5_5763

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_8_5762
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_8 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(8),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_8_5762

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_9_5761
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_9 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(9),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_9_5761

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_10_5760
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_10 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(10),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_10_5760

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_11_5759
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_11 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(11),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_11_5759

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_13_5758
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_13 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(13),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_13_5758

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_14_5757
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_14 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(14),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_14_5757

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_12_5756
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_12 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(12),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_12_5756

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_15_5755
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_15 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(15),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_15_5755

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_16_5754
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_16 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(16),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_16_5754

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_17_5753
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_17 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(17),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_17_5753

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_18_5752
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_18 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(18),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_18_5752

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_20_5751
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_20 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(20),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_20_5751

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_21_5750
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_21 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(21),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_21_5750

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_19_5749
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_19 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(19),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_19_5749

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_22_5748
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_22 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(22),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_22_5748

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_23_5747
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_23 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(23),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_23_5747

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_24_5746
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_24 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(24),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_24_5746

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_25_5745
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_25 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(25),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_25_5745

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_26_5744
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_26 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(26),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_26_5744

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_27 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_27_5743
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_27_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_27 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(27),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_27_5743

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_28 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_28_5742
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_28_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_28 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(28),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_28_5742

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_29 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_29_5741
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_29_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_29 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(29),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_29_5741

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_30 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_30_5740
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_30_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_30 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(30),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_30_5740

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_31 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_31_5739
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_31_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_31 : 
SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => BU2_divide_by_zero,
      A1 => BU2_divide_by_zero,
      A2 => BU2_divide_by_zero,
      A3 => BU2_divide_by_zero,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(31),
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_Mshreg_opt_has_pipe_first_q_31_5739

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_32_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_Mshreg_opt_has_pipe_pipe_32_0_1_5738,
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_32(0)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_Mshreg_opt_has_pipe_pipe_32_0_1 : SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_rfd,
      A1 => BU2_divide_by_zero,
      A2 => NlwRenamedSig_OI_rfd,
      A3 => NlwRenamedSig_OI_rfd,
      CLK => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_Mshreg_opt_has_pipe_pipe_32_0_0_5737,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_Mshreg_opt_has_pipe_pipe_32_0_1_5738
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_Mshreg_opt_has_pipe_pipe_32_0_0 : SRLC16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_rfd,
      A1 => NlwRenamedSig_OI_rfd,
      A2 => NlwRenamedSig_OI_rfd,
      A3 => NlwRenamedSig_OI_rfd,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_first_q(0),
      Q => 
NLW_BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_Mshreg_opt_has_pipe_pipe_32_0_0_Q_UNCONNECTED
,
      Q15 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_Mshreg_opt_has_pipe_pipe_32_0_0_5737
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_32_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_Mshreg_opt_has_pipe_pipe_32_1_1_5736,
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_32(1)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_Mshreg_opt_has_pipe_pipe_32_1_1 : SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_rfd,
      A1 => BU2_divide_by_zero,
      A2 => NlwRenamedSig_OI_rfd,
      A3 => NlwRenamedSig_OI_rfd,
      CLK => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_Mshreg_opt_has_pipe_pipe_32_1_0_5735,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_Mshreg_opt_has_pipe_pipe_32_1_1_5736
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_Mshreg_opt_has_pipe_pipe_32_1_0 : SRLC16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_rfd,
      A1 => NlwRenamedSig_OI_rfd,
      A2 => NlwRenamedSig_OI_rfd,
      A3 => NlwRenamedSig_OI_rfd,
      CLK => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_first_q(1),
      Q => 
NLW_BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_Mshreg_opt_has_pipe_pipe_32_1_0_Q_UNCONNECTED
,
      Q15 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_Mshreg_opt_has_pipe_pipe_32_1_0_5735
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_31_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_30_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(31)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_30_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_29_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(30)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_29_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_28_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(29)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_28_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_27_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(28)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_27_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_26_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(27)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_26_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(26)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_25_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(25)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_24_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(24)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_23_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(23)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_22_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(22)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_21_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(21)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_20_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(20)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_19_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(19)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_18_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(18)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_17_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(17)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_16_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(16)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_15_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(15)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_14_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(14)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_13_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(13)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_12_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(12)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_11_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(11)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_10_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(10)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_9_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(9)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_8_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(8)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_7_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(7)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_6_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(6)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_5_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(5)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_4_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(4)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_3_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(3)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_2_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(2)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi_1_1_INV_0 : INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(1)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(30)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(29)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(28)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(27)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(26)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(25)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(24)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(23)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(22)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(21)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(20)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(19)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(18)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(17)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(16)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(15)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(14)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(13)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(12)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(11)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(10)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(9)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(8)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(7)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(6)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(5)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(4)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(3)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(2)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(1)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_inv_o1_INV_0 : 
INV
    port map (
      I => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(0)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_32(0),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_4_5734
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_32(1),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_4_5730
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_32(1),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_3_5729
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_32(0),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_3_5733
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_32(0),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_2_5731
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_32(1),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_2_5732
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_32(0),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_1_5724
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_32(1),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_1_5725
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_0_rt : 
LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(0)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_0_rt_5722
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_0_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(0)
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_0_rt_5650
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_0_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => divisor_3(0),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_0_rt_281
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_0_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => dividend_2(0),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_0_rt_211
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a251 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(31),
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(0),
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(31)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a241 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(30),
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(0),
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(30)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a221 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(29),
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(0),
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(29)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a211 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(28),
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(0),
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(28)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a201 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(27),
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(0),
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(27)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a191 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(26),
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(0),
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(26)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a181 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(25),
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(0),
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(25)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a171 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(24),
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(0),
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(24)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a161 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(23),
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(0),
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(23)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a151 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(22),
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(0),
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(22)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a141 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(21),
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(0),
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(21)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a131 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(20),
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(0),
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(20)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a111 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(19),
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(0),
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(19)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a101 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(18),
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(0),
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(18)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a91 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(17),
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(0),
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(17)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a81 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(16),
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(0),
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(16)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a71 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(15),
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(0),
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(15)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a61 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(14),
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(0),
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(14)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a51 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(13),
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_4_5730,
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(0),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(13)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a41 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(12),
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_4_5730,
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(0),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(12)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a35 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(11),
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_4_5734,
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_4_5730,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(11)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a26 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(10),
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_4_5734,
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_4_5730,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(10)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a341 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(9)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_3_5733,
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_3_5729,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(9)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a331 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(8)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_3_5733,
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_3_5729,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(8)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a321 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(7)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_3_5733,
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_3_5729,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(7)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a311 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(6)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_3_5733,
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_3_5729,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(6)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a301 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(5)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_2_5731,
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_2_5732,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(5)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a291 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(4)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_2_5731,
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_2_5732,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(4)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a281 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(3)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_2_5731,
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_2_5732,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(3)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a231 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(2)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_2_5731,
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_2_5732,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(2)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Mmux_simp_addp_a121 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(1)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_2_5731,
      I2 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_2_5732,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(1)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Mmux_simp_addp_a261 : 
LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(9)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(9)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Mmux_simp_addp_a251 : 
LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(8)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(8)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Mmux_simp_addp_a241 : 
LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(7)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(7)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Mmux_simp_addp_a231 : 
LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(6)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_4_5730,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(6)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Mmux_simp_addp_a221 : 
LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(5)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_4_5730,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(5)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Mmux_simp_addp_a211 : 
LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(4)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_4_5730,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(4)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Mmux_simp_addp_a201 : 
LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(3)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_4_5730,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(3)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Mmux_simp_addp_a191 : 
LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(2)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_3_5729,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(2)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Mmux_simp_addp_a161 : 
LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(23)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(23)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Mmux_simp_addp_a151 : 
LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(22)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(22)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Mmux_simp_addp_a141 : 
LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(21)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(21)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Mmux_simp_addp_a131 : 
LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(20)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(20)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Mmux_simp_addp_a121 : 
LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(1)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_3_5729,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(1)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Mmux_simp_addp_a111 : 
LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(19)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(19)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Mmux_simp_addp_a101 : 
LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(18)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(18)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Mmux_simp_addp_a91 : 
LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(17)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(17)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Mmux_simp_addp_a81 : 
LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(16)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(16)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Mmux_simp_addp_a71 : 
LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(15)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(15)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Mmux_simp_addp_a61 : 
LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(14)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(14)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Mmux_simp_addp_a51 : 
LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(13)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(13)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Mmux_simp_addp_a41 : 
LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(12)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(12)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Mmux_simp_addp_a31 : 
LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(11)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(11)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Mmux_simp_addp_a27 : 
LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(10)
,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(10)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum251 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(9),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(9)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum241 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(8),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(8)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum231 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(7),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(7)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum221 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(6),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(6)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum211 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(5),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(5)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum201 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(4),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(4)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum191 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(3),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(3)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum181 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(2),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(2)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum161 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(23),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(23)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum151 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(22),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(22)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum141 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(21),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(21)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum131 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(20),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(20)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum121 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(1),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(1)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum111 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(19),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(19)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum101 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(18),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(18)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum91 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(17),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(17)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum81 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(16),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(16)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum71 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(15),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(15)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum61 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(14),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(14)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum51 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(13),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(13)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum41 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(12),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(12)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum31 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(11),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(11)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum26 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(10),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(10)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_Mmux_i_simple_model_halfsum17 : 
LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(0),
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(0)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_27_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_28_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_29_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT3
    generic map(
      INIT => X"69"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_30_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      I2 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_1 : 
LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_31_Q
,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_inv_o1 : LUT1
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_inv_o
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Mmux_simp_addp_a251 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => divisor_3(9),
      I1 => divisor_3(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(9)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Mmux_simp_addp_a241 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => divisor_3(8),
      I1 => divisor_3(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(8)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Mmux_simp_addp_a231 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => divisor_3(7),
      I1 => divisor_3(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(7)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Mmux_simp_addp_a221 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => divisor_3(6),
      I1 => divisor_3(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(6)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Mmux_simp_addp_a211 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => divisor_3(5),
      I1 => divisor_3(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(5)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Mmux_simp_addp_a201 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => divisor_3(4),
      I1 => divisor_3(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(4)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Mmux_simp_addp_a191 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => divisor_3(3),
      I1 => divisor_3(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(3)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Mmux_simp_addp_a181 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => divisor_3(2),
      I1 => divisor_3(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(2)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Mmux_simp_addp_a151 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => divisor_3(22),
      I1 => divisor_3(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(22)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Mmux_simp_addp_a141 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => divisor_3(21),
      I1 => divisor_3(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(21)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Mmux_simp_addp_a131 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => divisor_3(20),
      I1 => divisor_3(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(20)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Mmux_simp_addp_a121 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => divisor_3(1),
      I1 => divisor_3(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(1)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Mmux_simp_addp_a111 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => divisor_3(19),
      I1 => divisor_3(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(19)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Mmux_simp_addp_a101 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => divisor_3(18),
      I1 => divisor_3(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(18)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Mmux_simp_addp_a91 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => divisor_3(17),
      I1 => divisor_3(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(17)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Mmux_simp_addp_a81 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => divisor_3(16),
      I1 => divisor_3(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(16)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Mmux_simp_addp_a71 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => divisor_3(15),
      I1 => divisor_3(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(15)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Mmux_simp_addp_a61 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => divisor_3(14),
      I1 => divisor_3(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(14)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Mmux_simp_addp_a51 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => divisor_3(13),
      I1 => divisor_3(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(13)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Mmux_simp_addp_a41 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => divisor_3(12),
      I1 => divisor_3(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(12)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Mmux_simp_addp_a31 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => divisor_3(11),
      I1 => divisor_3(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(11)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Mmux_simp_addp_a26 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => divisor_3(10),
      I1 => divisor_3(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(10)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a331 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(9),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(9)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a321 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(8),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(8)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a311 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(7),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(7)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a301 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(6),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(6)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a291 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(5),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(5)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a281 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(4),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(4)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a271 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(3),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(3)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a241 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(30),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(30)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a231 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(2),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(2)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a221 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(29),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(29)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a211 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(28),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(28)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a201 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(27),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(27)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a191 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(26),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(26)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a181 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(25),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(25)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a171 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(24),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(24)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a161 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(23),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(23)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a151 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(22),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(22)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a141 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(21),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(21)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a131 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(20),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(20)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a121 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(1),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(1)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a111 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(19),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(19)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a101 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(18),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(18)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a91 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(17),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(17)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a81 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(16),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(16)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a71 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(15),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(15)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a61 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(14),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(14)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a51 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(13),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(13)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a41 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(12),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(12)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a34 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(11),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(11)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Mmux_simp_addp_a25 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => dividend_2(10),
      I1 => dividend_2(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(10)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_Mxor_quot_det_xo_0_1 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0_1_5724,
      I1 => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1_1_5725,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_quot_det
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(0),
      Q => fractional_5(0)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(1),
      Q => fractional_5(1)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(2),
      Q => fractional_5(2)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(3),
      Q => fractional_5(3)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(4),
      Q => fractional_5(4)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(5),
      Q => fractional_5(5)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(6),
      Q => fractional_5(6)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(7),
      Q => fractional_5(7)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_8 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(8),
      Q => fractional_5(8)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_9 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(9),
      Q => fractional_5(9)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_10 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(10),
      Q => fractional_5(10)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_11 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(11),
      Q => fractional_5(11)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_12 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(12),
      Q => fractional_5(12)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_13 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(13),
      Q => fractional_5(13)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_14 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(14),
      Q => fractional_5(14)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_15 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(15),
      Q => fractional_5(15)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_16 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(16),
      Q => fractional_5(16)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_17 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(17),
      Q => fractional_5(17)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_18 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(18),
      Q => fractional_5(18)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_19 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(19),
      Q => fractional_5(19)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_20 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(20),
      Q => fractional_5(20)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_21 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(21),
      Q => fractional_5(21)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_22 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(22),
      Q => fractional_5(22)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_q_i_23 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(23),
      Q => fractional_5(23)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_0_Q : 
MUXCY
    port map (
      CI => BU2_divide_by_zero,
      DI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1),
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_0_rt_5722
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(0)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_0_Q : 
XORCY
    port map (
      CI => BU2_divide_by_zero,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_0_rt_5722
,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(0)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_1_Q : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(0),
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(1),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(1)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_1_Q : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(0),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(1)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_2_Q : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(1),
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(2),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(2)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_2_Q : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(1),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(2),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(2)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_3_Q : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(2),
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(3),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(3)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_3_Q : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(2),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(3),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(3)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_4_Q : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(3),
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(4),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(4)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_4_Q : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(3),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(4),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(4)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_5_Q : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(4),
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(5),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(5)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_5_Q : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(4),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(5),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(5)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_6_Q : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(5),
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(6),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(6)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_6_Q : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(5),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(6),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(6)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_7_Q : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(6),
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(7),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(7)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_7_Q : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(6),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(7),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(7)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_8_Q : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(7),
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(8),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(8)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_8_Q : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(7),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(8),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(8)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_9_Q : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(8),
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(9),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(9)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_9_Q : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(8),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(9),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(9)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_10_Q : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(9),
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(10),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(10)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_10_Q : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(9),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(10),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(10)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_11_Q : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(10),
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(11),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(11)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_11_Q : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(10),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(11),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(11)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_12_Q : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(11),
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(12),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(12)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_12_Q : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(11),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(12),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(12)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_13_Q : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(12),
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(13),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(13)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_13_Q : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(12),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(13),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(13)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_14_Q : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(13),
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(14),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(14)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_14_Q : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(13),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(14),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(14)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_15_Q : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(14),
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(15),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(15)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_15_Q : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(14),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(15),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(15)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_16_Q : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(15),
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(16),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(16)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_16_Q : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(15),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(16),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(16)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_17_Q : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(16),
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(17),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(17)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_17_Q : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(16),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(17),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(17)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_18_Q : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(17),
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(18),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(18)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_18_Q : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(17),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(18),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(18)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_19_Q : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(18),
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(19),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(19)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_19_Q : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(18),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(19),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(19)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_20_Q : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(19),
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(20),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(20)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_20_Q : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(19),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(20),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(20)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_21_Q : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(20),
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(21),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(21)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_21_Q : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(20),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(21),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(21)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy_22_Q : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(21),
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(22),
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(22)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_22_Q : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(21),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(22),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(22)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_xor_23_Q : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_Madd_s_i_cy(22),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_simp_addp_a(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_remd_not_fract_cmp_remd_twos_comp_s_i(23)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(0),
      Q => quotient_4(0)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(1),
      Q => quotient_4(1)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(2),
      Q => quotient_4(2)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(3),
      Q => quotient_4(3)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(4),
      Q => quotient_4(4)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(5),
      Q => quotient_4(5)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(6),
      Q => quotient_4(6)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(7),
      Q => quotient_4(7)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_8 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(8),
      Q => quotient_4(8)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_9 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(9),
      Q => quotient_4(9)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_10 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(10),
      Q => quotient_4(10)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_11 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(11),
      Q => quotient_4(11)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_12 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(12),
      Q => quotient_4(12)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_13 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(13),
      Q => quotient_4(13)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_14 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(14),
      Q => quotient_4(14)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_15 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(15),
      Q => quotient_4(15)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_16 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(16),
      Q => quotient_4(16)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_17 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(17),
      Q => quotient_4(17)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_18 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(18),
      Q => quotient_4(18)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_19 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(19),
      Q => quotient_4(19)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_20 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(20),
      Q => quotient_4(20)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_21 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(21),
      Q => quotient_4(21)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_22 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(22),
      Q => quotient_4(22)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_23 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(23),
      Q => quotient_4(23)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_24 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(24),
      Q => quotient_4(24)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_25 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(25),
      Q => quotient_4(25)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_26 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(26),
      Q => quotient_4(26)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_27 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(27),
      Q => quotient_4(27)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_28 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(28),
      Q => quotient_4(28)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_29 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(29),
      Q => quotient_4(29)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_30 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(30),
      Q => quotient_4(30)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_q_i_31 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(31),
      Q => quotient_4(31)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_0_Q : MUXCY
    port map (
      CI => BU2_divide_by_zero,
      DI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_quot_det,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_0_rt_5650,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(0)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_0_Q : XORCY
    port map (
      CI => BU2_divide_by_zero,
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_0_rt_5650,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(0)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_1_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(0),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(1)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_1_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(0),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(1)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_2_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(1),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(2),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(2)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_2_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(1),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(2),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(2)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_3_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(2),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(3),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(3)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_3_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(2),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(3),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(3)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_4_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(3),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(4),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(4)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_4_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(3),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(4),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(4)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_5_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(4),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(5),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(5)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_5_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(4),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(5),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(5)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_6_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(5),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(6),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(6)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_6_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(5),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(6),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(6)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_7_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(6),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(7),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(7)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_7_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(6),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(7),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(7)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_8_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(7),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(8),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(8)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_8_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(7),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(8),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(8)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_9_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(8),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(9),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(9)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_9_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(8),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(9),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(9)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_10_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(9),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(10),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(10)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_10_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(9),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(10),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(10)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_11_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(10),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(11),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(11)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_11_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(10),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(11),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(11)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_12_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(11),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(12),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(12)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_12_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(11),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(12),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(12)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_13_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(12),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(13),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(13)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_13_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(12),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(13),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(13)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_14_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(13),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(14),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(14)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_14_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(13),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(14),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(14)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_15_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(14),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(15),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(15)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_15_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(14),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(15),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(15)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_16_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(15),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(16),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(16)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_16_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(15),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(16),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(16)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_17_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(16),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(17),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(17)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_17_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(16),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(17),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(17)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_18_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(17),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(18),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(18)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_18_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(17),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(18),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(18)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_19_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(18),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(19),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(19)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_19_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(18),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(19),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(19)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_20_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(19),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(20),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(20)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_20_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(19),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(20),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(20)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_21_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(20),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(21),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(21)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_21_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(20),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(21),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(21)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_22_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(21),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(22),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(22)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_22_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(21),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(22),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(22)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_23_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(22),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(23)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_23_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(22),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(23)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_24_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(23),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(24),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(24)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_24_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(23),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(24),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(24)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_25_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(24),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(25),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(25)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_25_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(24),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(25),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(25)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_26_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(25),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(26),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(26)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_26_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(25),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(26),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(26)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_27_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(26),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(27),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(27)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_27_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(26),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(27),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(27)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_28_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(27),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(28),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(28)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_28_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(27),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(28),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(28)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_29_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(28),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(29),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(29)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_29_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(28),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(29),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(29)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy_30_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(29),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(30),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(30)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_30_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(29),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(30),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(30)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_xor_31_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_Madd_s_i_cy(30),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_simp_addp_a(31),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_signed_output_cmp_quot_twos_comp_s_i(31)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(0)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(0)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(1)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(1)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(2)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(2)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(3)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(3)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(4)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(4)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(5)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(5)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(6)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(6)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(7)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(7)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(8)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(8)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(9)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(9)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(10)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(10)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(11)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(11)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(12)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(12)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(13)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(13)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(14)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(14)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(15)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(15)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(16)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(16)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(17)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(17)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(18)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(18)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(19)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(19)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(20)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(20)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(21)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(21)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(22)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(22)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(23)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(23)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(24)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q(24)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(24)
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_0_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(0),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(0)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_1_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(1),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(1)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_2_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(2),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(2)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_3_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(3),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(3)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_4_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(4),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(4)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_5_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(5),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(5)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_6_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(6),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(6)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_7_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(7),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(7)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_8_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(8),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(8)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_9_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(9),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(9)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_10_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(10),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_0
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(10)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_11_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(11),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(11)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_12_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(12),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(12)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_13_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(13),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(13)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_14_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(14),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(14)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_15_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(15),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(15)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_16_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(16),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(16)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_17_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(17),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(17)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_18_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(18),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(18)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_19_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(19),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(19)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_20_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(20),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(20)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_21_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(21),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(21)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_22_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(22),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(22)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_i_gt_1_multandgen_23_carrymultand : 
MULT_AND
    port map (
      I0 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(23),
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(23)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_bypass_i_bypass_other_i_di_b_variable_multandtop_carrymultand : 
MULT_AND
    port map (
      I0 => BU2_divide_by_zero,
      I1 => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      LO => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(24)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_divide_by_zero,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(0)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(0)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(0)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_divide_by_zero,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(0)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(0)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(0)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(1)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(1)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(1)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(1)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(2)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(2)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(2)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(2)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(3)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(3)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(3)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(3)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(4)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(4)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(4)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(4)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(5)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(5)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(5)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(5)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(6)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(6)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(6)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(6)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(7)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(7)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(7)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(7)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(8)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(8)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(8)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(8)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(9)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(9)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(9)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(9)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(10)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(10)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(10)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(10)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(11)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(11)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(11)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(11)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(12)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(12)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(12)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(12)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(13)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(13)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(13)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(13)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(14)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(14)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(14)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(14)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(15)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(15)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(15)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(15)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(16)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(16)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(16)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(16)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(17)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(17)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(17)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(17)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(18)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(18)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(18)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(18)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(19)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(19)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(19)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(19)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(20)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(20)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(20)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(20)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(21)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(21)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(21)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(21)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(22)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(22)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(22)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(22)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(23)
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(23)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(23)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(23)
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_di(24)
,
      S => BU2_divide_by_zero,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(24)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(23)
,
      LI => BU2_divide_by_zero,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(24)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(0)
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(1)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(1)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(1)
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(2)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(2)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(2)
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(3)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(3)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(3)
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(4)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(4)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(4)
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(5)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(5)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(5)
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(6)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(6)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(6)
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(7)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(7)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(7)
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(8)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(8)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(8)
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(9)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(9)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(9)
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(10)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(10)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(10)
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(11)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(11)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(11)
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(12)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(12)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(12)
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(13)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(13)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(13)
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(14)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(14)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(14)
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(15)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(15)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(15)
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(16)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(16)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(16)
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(17)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(17)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(17)
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(18)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(18)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(18)
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(19)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(19)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(19)
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(20)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(20)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(20)
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(21)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(21)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(21)
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(22)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(22)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple(22)
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum(23)
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_remd_output_adsu_sel2_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple(23)

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_26 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_26_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_27 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_26_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_27_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_28 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_27_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_28_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_29 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_28_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_29_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_30 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_29_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_30_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_26 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_26_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_27 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_26_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_27_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_28 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_27_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_28_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_29 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_28_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_29_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_26 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_26_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_27 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_26_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_27_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_28 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_27_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_28_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_26 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_26_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_27 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_26_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_27_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_26 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_26_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_25_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_27 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_27_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_27_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_27 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_27_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_27_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_28 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_28_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_28_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_27 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_27_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_27_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_28 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_28_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_28_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_29 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_29_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_29_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_27 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_27_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_27_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_28 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_28_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_28_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_29 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_29_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_29_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_30 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_30_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_30_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(30),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(30),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(29),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(29),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(28),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(28),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(27),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(27),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(26),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(26),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(25),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(25),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(24),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(24),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(23),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(23),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(22),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(22),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(21),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(21),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(20),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(20),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(19),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(19),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(18),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(18),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(17),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(17),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(16),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(16),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(15),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(15),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(14),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(14),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(13),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(13),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(12),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(12),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(11),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(11),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(10),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(10),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(9),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(9),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(8),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(8),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(7),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(7),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(6),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_24_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(6),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(5),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_25_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(5),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(4),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_26_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(4),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(3),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_27_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(3),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(2),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_28_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(2),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(1),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_29_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(1),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(0),
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_30_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_inv_o(0),
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_23_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_0_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_1_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_2_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_3_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_4_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_5_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_6_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_7_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_8_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_9_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_10_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_11_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_12_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_13_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_14_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_15_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_16_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_17_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_18_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_19_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_20_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_21_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_22_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_24_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_c_out_i_simple_add_q_cout_q_c_outreg_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_need_mux_carrymux0 : 
MUXCY
    port map (
      CI => NlwRenamedSig_OI_rfd,
      DI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_31_Q
,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_carryxor0 : 
XORCY
    port map (
      CI => NlwRenamedSig_OI_rfd,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_0_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_muxtop_carrymuxtop : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      DI => BU2_divide_by_zero,
      S => NlwRenamedSig_OI_rfd,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carrymux : 
MUXCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      DI => BU2_divide_by_zero,
      S => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_1_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_0_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_1_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_2_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_1_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_2_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_3_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_2_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_3_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_4_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_3_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_4_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_5_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_4_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_5_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_6_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_5_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_6_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_7_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_6_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_7_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_8_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_7_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_8_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_9_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_8_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_9_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_10_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_9_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_10_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_11_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_10_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_11_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_12_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_11_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_12_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_13_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_12_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_13_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_14_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_13_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_14_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_15_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_14_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_15_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_16_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_15_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_16_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_17_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_16_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_17_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_18_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_17_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_18_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_19_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_18_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_19_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_20_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_19_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_20_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_21_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_20_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_21_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_22_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_21_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_22_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carrychaingen_23_carryxor : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_22_Q
,
      LI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_halfsum_23_Q
,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_simple_model_i_gt_1_carryxortop : 
XORCY
    port map (
      CI => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_carry_simple_23_Q
,
      LI => NlwRenamedSig_OI_rfd,
      O => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_sum_simple_24_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_8_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_9_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_10_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_11_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_12_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_13_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_14_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_15_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_16_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_17_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_18_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_19_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_20_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_21_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_22_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_23_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_0 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(0)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(1)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(2)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(3)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(4)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(5)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(6)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_7_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(7)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_8 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_8_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(8)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_9 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_9_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(9)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_10 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_10_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(10)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_11 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_11_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(11)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_12 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_12_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(12)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_13 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_13_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(13)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_14 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_14_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(14)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_15 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_15_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(15)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_16 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_16_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(16)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_17 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_17_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(17)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_18 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_18_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(18)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_19 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_19_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(19)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_20 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_20_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(20)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_21 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_21_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(21)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_22 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_22_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(22)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q_23 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_divisor_gen_divisor_dc1_del_divisor_msbs_opt_has_pipe_first_q_23_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_final_div_del_end_divisor_opt_has_pipe_first_q(23)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_adder_gen_reg_req_adsu_mod_inv_o,
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(0)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(1),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(1)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(2),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(2)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(3),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(3)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(4),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(4)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(5),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(5)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(6),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(6)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(7),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(7)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_8 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(8),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(8)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_9 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(9),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(9)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_10 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(10),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(10)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_11 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(11),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(11)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_12 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(12),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(12)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_13 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(13),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(13)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_14 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(14),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(14)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_15 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(15),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(15)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_16 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(16),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(16)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_17 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(17),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(17)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_18 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(18),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(18)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_19 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(19),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(19)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_20 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(20),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(20)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_21 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(21),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(21)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_22 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(22),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(22)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_23 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(23),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(23)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_24 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(24),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(24)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_25 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(25),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(25)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_26 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(26),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(26)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_27 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(27),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(27)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_28 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(28),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(28)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_29 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(29),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(29)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_30 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(30),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(30)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q_31 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_qpi(31),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_reg_quot_out_reg_quot_opt_has_pipe_first_q(31)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_31_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_0_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_1_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_2_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_3_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_4_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_5_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_6_adder_gen_reg_req_adsu_mod_add1_no_pipelining_the_addsub_i_lut4_i_lut4_addsub_i_q_i_simple_qreg_opt_has_pipe_first_q_24_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_7_quot_gen_quot_reg_quot_out_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_6_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_24_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_5_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_25_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_4_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_26_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_3_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_27_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_2_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_28_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_1_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0 : 
FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_29_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q
,
      Q => 
BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_divider_blk_div_loop_30_num_stages_numerator_gen_del_numer_opt_has_pipe_first_q_0_Q

    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_first_q_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_msb_divisor_sync_opt_has_pipe_first_q,
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_first_q(0)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_first_q_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_msb_dividend_sync_opt_has_pipe_first_q,
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_first_q(1)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_32(0),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(0)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_32(1),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_sign_pipe_opt_has_pipe_pipe_33(1)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_0_Q : MUXCY
    port map (
      CI => BU2_divide_by_zero,
      DI => divisor_3(23),
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_0_rt_281,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(0)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_0_Q : XORCY
    port map (
      CI => BU2_divide_by_zero,
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_0_rt_281,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(0)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_1_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(0),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(1)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_1_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(0),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(1)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_2_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(1),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(2),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(2)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_2_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(1),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(2),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(2)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_3_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(2),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(3),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(3)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_3_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(2),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(3),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(3)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_4_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(3),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(4),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(4)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_4_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(3),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(4),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(4)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_5_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(4),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(5),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(5)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_5_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(4),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(5),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(5)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_6_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(5),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(6),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(6)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_6_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(5),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(6),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(6)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_7_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(6),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(7),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(7)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_7_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(6),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(7),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(7)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_8_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(7),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(8),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(8)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_8_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(7),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(8),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(8)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_9_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(8),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(9),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(9)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_9_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(8),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(9),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(9)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_10_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(9),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(10),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(10)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_10_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(9),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(10),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(10)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_11_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(10),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(11),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(11)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_11_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(10),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(11),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(11)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_12_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(11),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(12),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(12)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_12_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(11),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(12),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(12)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_13_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(12),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(13),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(13)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_13_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(12),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(13),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(13)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_14_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(13),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(14),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(14)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_14_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(13),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(14),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(14)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_15_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(14),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(15),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(15)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_15_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(14),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(15),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(15)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_16_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(15),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(16),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(16)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_16_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(15),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(16),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(16)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_17_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(16),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(17),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(17)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_17_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(16),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(17),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(17)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_18_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(17),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(18),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(18)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_18_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(17),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(18),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(18)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_19_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(18),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(19),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(19)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_19_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(18),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(19),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(19)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_20_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(19),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(20),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(20)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_20_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(19),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(20),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(20)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_21_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(20),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(21),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(21)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_21_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(20),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(21),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(21)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy_22_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(21),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(22),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(22)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_22_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(21),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_simp_addp_a(22),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(22)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_xor_23_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_Madd_s_i_cy(22),
      LI => BU2_divide_by_zero,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_divisor_twos_comp_s_i(23)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_0_Q : MUXCY
    port map (
      CI => BU2_divide_by_zero,
      DI => dividend_2(31),
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_0_rt_211,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(0)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_0_Q : XORCY
    port map (
      CI => BU2_divide_by_zero,
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_0_rt_211,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(0)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_1_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(0),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(1)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_1_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(0),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(1),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(1)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_2_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(1),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(2),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(2)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_2_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(1),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(2),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(2)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_3_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(2),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(3),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(3)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_3_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(2),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(3),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(3)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_4_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(3),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(4),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(4)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_4_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(3),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(4),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(4)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_5_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(4),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(5),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(5)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_5_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(4),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(5),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(5)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_6_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(5),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(6),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(6)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_6_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(5),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(6),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(6)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_7_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(6),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(7),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(7)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_7_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(6),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(7),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(7)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_8_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(7),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(8),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(8)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_8_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(7),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(8),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(8)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_9_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(8),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(9),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(9)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_9_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(8),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(9),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(9)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_10_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(9),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(10),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(10)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_10_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(9),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(10),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(10)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_11_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(10),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(11),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(11)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_11_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(10),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(11),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(11)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_12_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(11),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(12),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(12)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_12_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(11),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(12),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(12)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_13_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(12),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(13),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(13)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_13_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(12),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(13),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(13)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_14_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(13),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(14),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(14)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_14_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(13),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(14),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(14)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_15_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(14),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(15),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(15)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_15_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(14),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(15),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(15)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_16_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(15),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(16),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(16)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_16_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(15),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(16),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(16)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_17_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(16),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(17),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(17)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_17_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(16),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(17),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(17)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_18_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(17),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(18),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(18)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_18_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(17),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(18),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(18)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_19_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(18),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(19),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(19)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_19_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(18),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(19),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(19)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_20_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(19),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(20),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(20)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_20_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(19),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(20),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(20)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_21_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(20),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(21),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(21)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_21_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(20),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(21),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(21)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_22_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(21),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(22),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(22)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_22_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(21),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(22),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(22)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_23_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(22),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(23)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_23_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(22),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(23),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(23)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_24_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(23),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(24),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(24)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_24_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(23),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(24),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(24)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_25_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(24),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(25),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(25)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_25_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(24),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(25),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(25)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_26_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(25),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(26),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(26)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_26_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(25),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(26),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(26)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_27_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(26),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(27),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(27)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_27_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(26),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(27),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(27)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_28_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(27),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(28),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(28)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_28_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(27),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(28),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(28)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_29_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(28),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(29),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(29)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_29_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(28),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(29),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(29)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy_30_Q : MUXCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(29),
      DI => BU2_divide_by_zero,
      S => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(30),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(30)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_30_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(29),
      LI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_simp_addp_a(30),
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(30)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_xor_31_Q : XORCY
    port map (
      CI => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_Madd_s_i_cy(30),
      LI => BU2_divide_by_zero,
      O => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sgned_input_cmp_dividend_twos_comp_s_i(31)
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_msb_divisor_sync_opt_has_pipe_first_q_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_msb_divisor_start_opt_has_pipe_first_q,
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_msb_divisor_sync_opt_has_pipe_first_q
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_msb_dividend_sync_opt_has_pipe_first_q_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_msb_dividend_start_opt_has_pipe_first_q,
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_msb_dividend_sync_opt_has_pipe_first_q
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_msb_divisor_start_opt_has_pipe_first_q_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => divisor_3(23),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_msb_divisor_start_opt_has_pipe_first_q
    );
  BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_msb_dividend_start_opt_has_pipe_first_q_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => dividend_2(31),
      Q => BU2_U0_i_synth_opt_i_nonzero_fract_i_synth_i_algo_r2_nr_i_sdivider_I_SYNTH_MODEL_sign_pipeline_msb_dividend_start_opt_has_pipe_first_q
    );
  BU2_XST_VCC : VCC
    port map (
      P => NlwRenamedSig_OI_rfd
    );
  BU2_XST_GND : GND
    port map (
      G => BU2_divide_by_zero
    );

end STRUCTURE;

-- synthesis translate_on
