mirror of
https://github.com/k3ng/k3ng_rotator_controller.git
synced 2024-12-26 00:01:11 +00:00
b1be2b7e6b
Added OPTION_STEPPER_MOTOR_USE_TIMER_ONE_INSTEAD_OF_FIVE for FEATURE_STEPPER_MOTOR. Also added TimerOne library to Github.
209 lines
7.8 KiB
C++
Executable File
209 lines
7.8 KiB
C++
Executable File
/*
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* Interrupt and PWM utilities for 16 bit Timer1 on ATmega168/328
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* Original code by Jesse Tane for http://labs.ideo.com August 2008
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* Modified March 2009 by Jérôme Despatis and Jesse Tane for ATmega328 support
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* Modified June 2009 by Michael Polli and Jesse Tane to fix a bug in setPeriod() which caused the timer to stop
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* Modified June 2011 by Lex Talionis to add a function to read the timer
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* Modified Oct 2011 by Andrew Richards to avoid certain problems:
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* - Add (long) assignments and casts to TimerOne::read() to ensure calculations involving tmp, ICR1 and TCNT1 aren't truncated
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* - Ensure 16 bit registers accesses are atomic - run with interrupts disabled when accessing
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* - Remove global enable of interrupts (sei())- could be running within an interrupt routine)
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* - Disable interrupts whilst TCTN1 == 0. Datasheet vague on this, but experiment shows that overflow interrupt
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* flag gets set whilst TCNT1 == 0, resulting in a phantom interrupt. Could just set to 1, but gets inaccurate
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* at very short durations
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* - startBottom() added to start counter at 0 and handle all interrupt enabling.
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* - start() amended to enable interrupts
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* - restart() amended to point at startBottom()
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* Modiied 7:26 PM Sunday, October 09, 2011 by Lex Talionis
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* - renamed start() to resume() to reflect it's actual role
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* - renamed startBottom() to start(). This breaks some old code that expects start to continue counting where it left off
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* See Google Code project http://code.google.com/p/arduino-timerone/ for latest
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*/
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#ifndef TIMERONE_cpp
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#define TIMERONE_cpp
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#include "TimerOne.h"
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TimerOne Timer1; // preinstatiate
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ISR(TIMER1_OVF_vect) // interrupt service routine that wraps a user defined function supplied by attachInterrupt
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{
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Timer1.isrCallback();
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}
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void TimerOne::initialize(long microseconds)
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{
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TCCR1A = 0; // clear control register A
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TCCR1B = _BV(WGM13); // set mode 8: phase and frequency correct pwm, stop the timer
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setPeriod(microseconds);
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}
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void TimerOne::setPeriod(long microseconds) // AR modified for atomic access
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{
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long cycles = (F_CPU / 2000000) * microseconds; // the counter runs backwards after TOP, interrupt is at BOTTOM so divide microseconds by 2
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if(cycles < RESOLUTION) clockSelectBits = _BV(CS10); // no prescale, full xtal
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else if((cycles >>= 3) < RESOLUTION) clockSelectBits = _BV(CS11); // prescale by /8
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else if((cycles >>= 3) < RESOLUTION) clockSelectBits = _BV(CS11) | _BV(CS10); // prescale by /64
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else if((cycles >>= 2) < RESOLUTION) clockSelectBits = _BV(CS12); // prescale by /256
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else if((cycles >>= 2) < RESOLUTION) clockSelectBits = _BV(CS12) | _BV(CS10); // prescale by /1024
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else cycles = RESOLUTION - 1, clockSelectBits = _BV(CS12) | _BV(CS10); // request was out of bounds, set as maximum
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oldSREG = SREG;
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cli(); // Disable interrupts for 16 bit register access
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ICR1 = pwmPeriod = cycles; // ICR1 is TOP in p & f correct pwm mode
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SREG = oldSREG;
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TCCR1B &= ~(_BV(CS10) | _BV(CS11) | _BV(CS12));
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TCCR1B |= clockSelectBits; // reset clock select register, and starts the clock
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}
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void TimerOne::setPwmDuty(char pin, int duty)
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{
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unsigned long dutyCycle = pwmPeriod;
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dutyCycle *= duty;
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dutyCycle >>= 10;
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oldSREG = SREG;
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cli();
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if(pin == 1 || pin == 9) OCR1A = dutyCycle;
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else if(pin == 2 || pin == 10) OCR1B = dutyCycle;
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SREG = oldSREG;
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}
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void TimerOne::pwm(char pin, int duty, long microseconds) // expects duty cycle to be 10 bit (1024)
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{
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if(microseconds > 0) setPeriod(microseconds);
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if(pin == 1 || pin == 9) {
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DDRB |= _BV(PORTB1); // sets data direction register for pwm output pin
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TCCR1A |= _BV(COM1A1); // activates the output pin
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}
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else if(pin == 2 || pin == 10) {
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DDRB |= _BV(PORTB2);
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TCCR1A |= _BV(COM1B1);
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}
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setPwmDuty(pin, duty);
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resume(); // Lex - make sure the clock is running. We don't want to restart the count, in case we are starting the second WGM
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// and the first one is in the middle of a cycle
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}
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void TimerOne::disablePwm(char pin)
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{
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if(pin == 1 || pin == 9) TCCR1A &= ~_BV(COM1A1); // clear the bit that enables pwm on PB1
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else if(pin == 2 || pin == 10) TCCR1A &= ~_BV(COM1B1); // clear the bit that enables pwm on PB2
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}
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void TimerOne::attachInterrupt(void (*isr)(), long microseconds)
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{
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if(microseconds > 0) setPeriod(microseconds);
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isrCallback = isr; // register the user's callback with the real ISR
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TIMSK1 = _BV(TOIE1); // sets the timer overflow interrupt enable bit
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// might be running with interrupts disabled (eg inside an ISR), so don't touch the global state
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// sei();
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resume();
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}
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void TimerOne::detachInterrupt()
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{
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TIMSK1 &= ~_BV(TOIE1); // clears the timer overflow interrupt enable bit
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// timer continues to count without calling the isr
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}
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void TimerOne::resume() // AR suggested
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{
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TCCR1B |= clockSelectBits;
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}
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void TimerOne::restart() // Depricated - Public interface to start at zero - Lex 10/9/2011
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{
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start();
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}
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void TimerOne::start() // AR addition, renamed by Lex to reflect it's actual role
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{
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unsigned int tcnt1;
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TIMSK1 &= ~_BV(TOIE1); // AR added
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GTCCR |= _BV(PSRSYNC); // AR added - reset prescaler (NB: shared with all 16 bit timers);
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oldSREG = SREG; // AR - save status register
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cli(); // AR - Disable interrupts
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TCNT1 = 0;
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SREG = oldSREG; // AR - Restore status register
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resume();
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do { // Nothing -- wait until timer moved on from zero - otherwise get a phantom interrupt
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oldSREG = SREG;
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cli();
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tcnt1 = TCNT1;
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SREG = oldSREG;
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} while (tcnt1==0);
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// TIFR1 = 0xff; // AR - Clear interrupt flags
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// TIMSK1 = _BV(TOIE1); // sets the timer overflow interrupt enable bit
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}
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void TimerOne::stop()
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{
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TCCR1B &= ~(_BV(CS10) | _BV(CS11) | _BV(CS12)); // clears all clock selects bits
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}
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unsigned long TimerOne::read() //returns the value of the timer in microseconds
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{ //rember! phase and freq correct mode counts up to then down again
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unsigned long tmp; // AR amended to hold more than 65536 (could be nearly double this)
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unsigned int tcnt1; // AR added
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oldSREG= SREG;
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cli();
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tmp=TCNT1;
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SREG = oldSREG;
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char scale=0;
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switch (clockSelectBits)
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{
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case 1:// no prescalse
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scale=0;
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break;
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case 2:// x8 prescale
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scale=3;
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break;
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case 3:// x64
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scale=6;
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break;
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case 4:// x256
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scale=8;
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break;
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case 5:// x1024
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scale=10;
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break;
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}
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do { // Nothing -- max delay here is ~1023 cycles. AR modified
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oldSREG = SREG;
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cli();
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tcnt1 = TCNT1;
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SREG = oldSREG;
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} while (tcnt1==tmp); //if the timer has not ticked yet
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//if we are counting down add the top value to how far we have counted down
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tmp = ( (tcnt1>tmp) ? (tmp) : (long)(ICR1-tcnt1)+(long)ICR1 ); // AR amended to add casts and reuse previous TCNT1
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return ((tmp*1000L)/(F_CPU /1000L))<<scale;
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}
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#endif |